Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is finally emerging as a mainstream semiconductor technology. Potential applications such as SRAM, lower power logic and RF IC have been demonstrated by major semiconductor companies. In this thesis, many remaining issues ranging from device physics to circuit modeling have been addressed. _out...[ Read more ]

Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is finally emerging as a mainstream semiconductor technology. Potential applications such as SRAM, lower power logic and RF IC have been demonstrated by major semiconductor companies. In this thesis, many remaining issues ranging from device physics to circuit modeling have been addressed.

The impacts of silicon film thickness and channel width scaling on Re-oxidized MESA isolation were studied. The subthreshold characteristics and narrow width effect are explained through the geometry of device edge resulted from the sidewall reoxidation.

Several major issues of floating body SOI MOSFET's are addressed in this thesis. The frequency dispersion of output resistance (R_out) in partially depleted device was studied. The effect is explained by the floating body potential fluctuation under the combined influence of hole accumulation in the neutral body and capacitive coupling. Next, capacitive coupling effect was studied theoretically and experimentally. The body charge model for bulk MOSFET was evaluated for its accuracy in predicting the coupling effect. A simple technique was also proposed to characterize the gate coupling factor.

Lastly, a new compact model suitable for circuit simulation of both Partially Depleted and Fully Depleted SOI MOSFET's was developed. A Dynamic Depletion Approach is proposed to model the automatic transition between different depletion modes. Though the joint effort of the graduate researchers in University of California at Berkeley and our group, the model has been installed into Berkeley SPICE 3f4 as BSIM3SOI. Charges and drain current are scaleable with buried oxide and silicon film thickness. Most of the SOI specific effects such as self-heating, parasitic bipolar, nonideal body contact and backgate effect are included. The C-V model is improved for better accuracy in capacitive coupling prediction. The model is now under evaluation by many companies and SEMATECH.