THESIS
1998
x, 121 leaves : ill. ; 30 cm
Abstract
With the advances in packaging technologies and increasing demand for high-speed and small size electronic circuits, Multichip Module (MCM) technology has been developed for high-speed and high-performance applications. However, due to the very limited accessibility to the module circuitry, testing for such a high density module is a complex and time consuming process. This thesis addresses the issues of assembled module interconnect testing in the context of boundary-scan architecture. The emphasis will be on the structural interconnect integrity testing as well as mechanical assembly defects detection....[
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With the advances in packaging technologies and increasing demand for high-speed and small size electronic circuits, Multichip Module (MCM) technology has been developed for high-speed and high-performance applications. However, due to the very limited accessibility to the module circuitry, testing for such a high density module is a complex and time consuming process. This thesis addresses the issues of assembled module interconnect testing in the context of boundary-scan architecture. The emphasis will be on the structural interconnect integrity testing as well as mechanical assembly defects detection.
In this thesis, the development of a low-cost test and diagnosis platform based on the IEEE Std 1149.1 boundary-scan testing methodology will be presented. Boundary-Scan is a structured design-for-testability (DFT) technique which can be used to simplify the testing of digital circuits, boards, and systems. A test chip containing the boundary-scan architecture has been fabricated using a 1.2μm n-well CMOS process. To demonstrate the prototype capabilities of the test system, a test evaluation module containing the boundary-scan test chips has been implemented. In view of interconnect faults detection and diagnosis, an efficient structural diagnostic approach has been proposed. While existing diagnosis schemes assume only simple bridging fault model, a more complex bridging short fault model in CMOS circuit environment is considered. Simulation results show that our approach performs very well when the short fault rate is very small. Limitations and further enhancements of the test system will also be discussed. We have also investigated the application of boundary-scan testing as part of the manufacturability assessment of the Flip Chip On Board (FCOB) assembly process. Assembly defects such as solder bumps opens and shorts could be detected and located.
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