Abstract
An automatic placement system with emphasis on technology independent methodology and device matching consideration for analog layout design is presented. A novel optimization approach based on circuit partitioning, simulated annealing and branch-and-bound algorithm is proposed to solve the placement problem. The move set used to generate perturbations for annealing is capable of arriving at any topological placement. The branch-and-bound is modified to take circuit performance into consideration. Results of seveal silicon proven designs generated by the system demonstrate an 8X cycle time reduction as compared to a manual approach.