Silicides have been widely used to reduce the parasitic resistances in silicon-based VLSI circuits, and as the novel self-aligned-silicide (salicide) technology in MOS devices. Nickel and Cobalt silicides (Nisi and CoSi₂) are two of the most promising silicides. _{2 2 2}...[ Read more ]

Silicides have been widely used to reduce the parasitic resistances in silicon-based VLSI circuits, and as the novel self-aligned-silicide (salicide) technology in MOS devices. Nickel and Cobalt silicides (Nisi and CoSi₂) are two of the most promising silicides.

In the first part of the work, stability of Co and Ni silicides on crystalline Si (c-Si), polycrystalline Si (poly-Si) and amorphous Si (a-Si) substrates have been studied. CoSi₂ shows low resistivity ([spacing tide]15[mu omega]-cm) on c-Si, poly-Si and a-Si after 650-900℃/30-60min long time anneal in N₂ or forming gas. Nisi has lo resistivity ([spacing tide]15[mu omega]-cm) on c-Si and poly-Si after 350-700℃/30- 60min anneal. On a-Si, however, Nisi has increasing resistivities and mixes with Nisi₂ and a-Si even at 400℃.

In the second part, stability of Ti, Co, Ni and Ti/Co silicides on poly-Si gate lines have been studied. On P-doped poly-Si, TiSi₂, CoSi₂ and Nisi lines show low resistivity ([spacing tide]15[mu omega]-cm) after 850, 800 and 700℃/lhour long time anneal respectively. The low resistivity is stable down to linewidths of around 0.43, 0.50 and 0.15 pm. 200Å of Ti-capping layer on Co has also been tested. The Ti cap layer seems to improve the resistivity stability of CoSi₂ down to around 0. lμm after 800℃/l hour anneal.

Finally, a new pure Nisi gate has been studied. The pure gate is found to maintain low resistivity ([spacing tide]15[mu omega]-cm) even after 900℃/lmin rapid thermal anneal. It is also stable on gate oxide as thin as 130Å after 700℃/lmin rapid thermal anneal. Using the pure gate, symmetrical threshold voltages have been obtained on both n-channel and p-channel MOS devices. The new dual gate technology can greatly help to improve the CMOS process and device performance.