In current computer communication network, it is dominated by two technologies, namely Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Connection-oriented ATM is the best for real-time services which require guaranteed quality-of-service like video conferencing. However, connectionless IP is more efficient than ATM for non real-time services like email. Currently, the major research challenge is on how to integrate ATM and IP into a single network efficiently. A novel network design, namely A/I Net is proposed to solve this problem. It is demonstrated by the realization of the center piece of the A/I Net architecture: the A/I Switch....[ Read more ]

In current computer communication network, it is dominated by two technologies, namely Asynchronous Transfer Mode (ATM) and Internet Protocol (IP). Connection-oriented ATM is the best for real-time services which require guaranteed quality-of-service like video conferencing. However, connectionless IP is more efficient than ATM for non real-time services like email. Currently, the major research challenge is on how to integrate ATM and IP into a single network efficiently. A novel network design, namely A/I Net is proposed to solve this problem. It is demonstrated by the realization of the center piece of the A/I Net architecture: the A/I Switch.

In this thesis, a VLSI implementation of a multistage self-routing ATM switch fabric which is one of the key components of the A/I Switch will be introduced. The size of the switch prototype is 16x16. The chip is designed to operate at a minimum frequency of 100MHz and the system is capable of handling the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16x16 switch is realized using four identical chips. It achieves high performance by utilizing distributed control and speed-up with input-output buffering technique. A priority structure, which supports four level, allows the delay sensitive ATM cells to be switched with the shortest latency. It also enables the non-interleaving routing scheme of IP cells. Results based on system simulations, which modeled random arrival process of ATM and IP traffic, show this architecture can achieve low cell loss rate if optimal buffers are provided.