Information network today can be classified into two modes of operations, datagram which is connectionless, and virtual circuit which is connection-oriented. For internet browsing, email and other non-real time applications, connectionless datagram such as IP is preferred because of its simplicity in transmission setup. For continuous stream of transmission like video conferencing which requires high quality real time transmission, a connection-oriented operation such as ATM should be used to guarantee stable network resources. ATM provides a faster transfer mechanism and its ability to support flexible multipoint communication make it probably the best protocol for boardband networking in the future. There is always a great interest in running a current protocol such as IP over ATM env...[ Read more ]

Information network today can be classified into two modes of operations, datagram which is connectionless, and virtual circuit which is connection-oriented. For internet browsing, email and other non-real time applications, connectionless datagram such as IP is preferred because of its simplicity in transmission setup. For continuous stream of transmission like video conferencing which requires high quality real time transmission, a connection-oriented operation such as ATM should be used to guarantee stable network resources. ATM provides a faster transfer mechanism and its ability to support flexible multipoint communication make it probably the best protocol for boardband networking in the future. There is always a great interest in running a current protocol such as IP over ATM environment. This will provide an easy bridge between current networking protocols and future ATM-only protocols. A new network architecture that integrates IP and ATM, namely the AINet, is proposed in this thesis.

AINet consists of ATM/P dual-traffic cell processors together with a multistage self-routing ATM switch fabric. A VLSI implementation of the ATM/P dual-traffic cell processor is introduced. The thesis stresses the architectural design of the ATM cell processing unit of the processor. A multi-queue shared buffer memory structure is proposed which enables a completely optimised cell memory usage. The chip runs at 100MHz with a 50MHz commercial SRAM chip as the cell memory. System simulation results obtained from injecting different ratios of ATM/P traffic show that the port processor works well with 155Mbps link and 1.6Gbps switch.