Broadband networks based on the Asynchronous Transfer Mode (ATM) standard are becoming more and more popular worldwide for their flexibility in providing an integrated transport of heterogeneous kinds of communication services. Research in ATM switching has been undertaken throughout the world for several years. A large number of ATM switch architectures have been proposed. ATM switch designs can be classified into two general categories, namely time switching and space switching. An important difference between time switching and space switching is the buffering scheme which specifies the location of cell storage in a switch. The buffering strategy has a great impact on the overall performance and the cost of the system. A pure input queuing switch yield a lower maximum throughput and...[ Read more ]

Broadband networks based on the Asynchronous Transfer Mode (ATM) standard are becoming more and more popular worldwide for their flexibility in providing an integrated transport of heterogeneous kinds of communication services. Research in ATM switching has been undertaken throughout the world for several years. A large number of ATM switch architectures have been proposed. ATM switch designs can be classified into two general categories, namely time switching and space switching. An important difference between time switching and space switching is the buffering scheme which specifies the location of cell storage in a switch. The buffering strategy has a great impact on the overall performance and the cost of the system. A pure input queuing switch yield a lower maximum throughput and a pure output queuing switch has design complexity and scalability problems. In order to achieve an acceptable performance level while avoiding the complexity problem associated with pure output queuing, many switch designs employ a combined input/output queuing strategy.

In this thesis, we investigated the optimum ways of dividing buffers between the input and the output queues of ATM switches. Firstly, we studied the ATM switches built with different space and time factors, but with the same maximum capacity. We developed an analytical model and derived the exact values of the space and time factors required to build ATM switches with the same maximum capacity, for both uncorrelated input traffic and correlated input traffic. We found that the optimum buffer division scheme is relatively insensitive to the (space, time) implementation but rather sensitive to the maximum switch capacity. We also found some other factors that influence the optimum points. Secondly, we proposed a scheme for non-interleaving packet transmission in an ATM environment and compared its implementation complexity with the interleaving scheme. We obtained the different optimum buffer division sensitivity to the speedup factor for these two transmission schemes. The conclusion is that using non-interleaving mode to implement the packet-based discarding leads to significantly less complexity but larger packet loss rate. Finally, we studied the performance improvement for the buffer-sharing scheme. That is, the input queue and the output queue of each port share a common buffer.