This master thesis presents the design of a 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers with good phase-noise performance....[ Read more ]

This master thesis presents the design of a 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers with good phase-noise performance.

Designing fully integrated frequency synthesizers for system integration is always desirable but most challenging. This first requirement is to achieve high frequency operation with reasonable power consumption. However, the most critical challenges for the frequency synthesizer are the phase-noise and spurious-tone performance. Finally, small chip area is essential to monolithic system integration.

The dual-loop design consists of two reference signals and two phase-locked loops (PLLs) in cascade configuration. Because of the dual-loop architecture, input frequencies of the two PLLs are scaled from 200 kHz to 1.6 MHz and 11.3 MHz. Therefore, the loop bandwidths of both PLLs can be increased, so that both switching time and chip area can be reduced.

Implemented in a 0.5 -μm CMOS technology and at 2-V supply voltage, the dual-loop frequency synthesizer has a low power consumption of 34 mW. At 900 MHz, the phase noise of the dual-loop design is less than -12 1.83 dBc/Hz at 600-kHz frequency offset. The spurious tones are -79.5 dBc @ 1.6MHz, -82.0 dBc @ 11.3MHz and -82.88 dBc @ 16MHz. The worst-case switching time is less than 830 μs. The chip area is 2.64 mm². However, the peak close-in phase noise is -65.67 dBc/Hz at 15-kHz frequency offset which is 15 dB worse than the specification of GSM 900.