In modern transceiver designs, a frequency synthesizer with good phase-noise performance is very important because it affects the efficiency of valuable air channel usage and sensitivity of small signals under the presence of large interference. Fast frequency switching is also required in many TDMA systems and frequency-hopping spread-spectrum systems. Other than these, low supply voltage, low power consumption and monolithic design are three important features of any modern analog circuits....[ Read more ]

In modern transceiver designs, a frequency synthesizer with good phase-noise performance is very important because it affects the efficiency of valuable air channel usage and sensitivity of small signals under the presence of large interference. Fast frequency switching is also required in many TDMA systems and frequency-hopping spread-spectrum systems. Other than these, low supply voltage, low power consumption and monolithic design are three important features of any modern analog circuits.

However, the above requirements are difficult to be achieved in traditional frequency synthesizer designs. To solve these problems, a new design of phase-locked loop frequency synthesizer is proposed. Instead of voltage or current domain, some signals in the phase-locked loop are manipulated in capacitance domain. A binary-weighted switchable-capacitor array is used to replace the digital-to-analog converter while two varactors connected in parallel replace the voltage adder. This design provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching and high immunity of substrate noise.

A prototype of a 1.5-V 900-Mhz monolithic CMOS fast-switching frequency synthesizer based on GSM specifications is designed and fabricated to demonstrate the idea. It consumes 30mW. The total chip area is 0.9 x 1.1 mm². The settling time is within 150us and phase noise is -118dBc/Hz at 600kHz offset. The ability of direct-digital modulation is also provided with the sigma-delta fractional-N architecture.