THESIS
2000
vi, 81 leaves : ill. ; 30 cm
Abstract
The constraints imposed by the present technology limit the maximum number of neural components that can be defined on a single chip and the number of wires for interconnections. In order to implement larger perceptive systems with more complex functionality, multi-chip architectures with efficient communication scheme are desirable. The address-event representation (AER) encodes analog signals using asynchronously produced fixed-height, fixed-width pulses, by temporal multiplexing the addresses of the firing neurons onto a single digital bus. This reduces drastically the number of physical interconnections required. Up to the present, most applications of the AER have been in feed-forward neural networks....[
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The constraints imposed by the present technology limit the maximum number of neural components that can be defined on a single chip and the number of wires for interconnections. In order to implement larger perceptive systems with more complex functionality, multi-chip architectures with efficient communication scheme are desirable. The address-event representation (AER) encodes analog signals using asynchronously produced fixed-height, fixed-width pulses, by temporal multiplexing the addresses of the firing neurons onto a single digital bus. This reduces drastically the number of physical interconnections required. Up to the present, most applications of the AER have been in feed-forward neural networks.
This thesis investigates the stability and functionality of a class of recurrent neural networks, where feedback interconnections are governed by the AER. In particular, we focus on a type of winner-take-all (WTA) network. WTA networks have been playing a very important role in the design of unsupervised learning neural networks, and various implementations have been proposed recently since the first hardware model by Lazzaro and his colleagues. Also, the WTA networks have close relationship with most of the recurrent cortical models in the primary visual cortex (Vl), from simple orientation-selectivity [4] to contour integration [5].
Based upon both theoretical analysis and intensive simulation results, we find that it is feasible to implement WTA networks in a pulse coupled manner. Criteria for selecting design parameters have been developed. We also compare the performances of different asynchronous pulse based communication schemes using the AER on the system level. Our results show that arbitration is the best choice for neuromorphic systems whose activity is sparse in space and in time. These results should be applicable to the implementation of the recurrent cortical competition and other complex networks with pulse coupled techniques. Pulse coupled neural networks are thus an efficient and feasible candidate for multi-chip architectures.
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