A high performance three-dimensional (3-D) CMOS integrated circuit has been successfully fabricated. The bottom layer transistors are fabricated on Silicon-on-Insulator (SOI) and top layer transistors are fabricated on Large-Grain Polysilicon-On-Insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of an amorphous silicon through nickel-seed Metal Induced Lateral Crystallization (MILC) at an elevated temperature....[ Read more ]

A high performance three-dimensional (3-D) CMOS integrated circuit has been successfully fabricated. The bottom layer transistors are fabricated on Silicon-on-Insulator (SOI) and top layer transistors are fabricated on Large-Grain Polysilicon-On-Insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of an amorphous silicon through nickel-seed Metal Induced Lateral Crystallization (MILC) at an elevated temperature.

To fabricate a high performance circuit, electron beam (e-beam) direct write technique is employed to define the channel area and gate electrode in sub-micron scales. Two new ideas are developed to improve the process. 1) The e-beam and optical resist mix-and-match technique demonstrates the improvement of process throughout. 2) A high-resolution positive e-beam resist enhances a negative resist resolution, so fine and dense bright-field pattern can be defined.

To demonstrate the feasibility of the MILC technology, single-gate thin film transistors have been fabricated. The understanding of the process and design limitation is critical and useful in novel layout and process design.

The first novel structure fabricated by the MILC technique is the gate-all-around transistor. It exhibits better electrical performance than the single gate transistors and effectively suppresses short channel effect.

A high performance and low power 3-D structure has been fabricated. The top layer LPSOI devices have similar electrical characteristics to the bottom layer SOI devices. Compared with the conventional 2-D CMOS SOI circuits, 3-D circuits such as, ring-oscillators, shift registers and SRAM cells, show significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.

The grain boundary distribution and surface roughness were observed using the Atomic Force Microscopy (AFM) and Secondary Electron Microscopy (SEM). A physical mobility model is developed to predict the polysilicon grain size within the MILC regions. The variation in electrical performance may be attributed to the grain boundary effect.