CMOS Active Pixel Sensor (APS) takes the advantage of the mature CMOS industry to compete with the Charge-Coupled Devices (CCD). The advantage of CMOS APS includes low supply voltage, high integration, and flexible functions. However, the scaling of conventional CMOS Active Pixel Sensors (APS) has been shown to be difficult. Besides process optimization issues, one of the major barrier in APS scaling is the limit on the available output swing at reduced power supply. Small output swing has an enormous impact on the signal-to-noise ratio and the dynamic range of the CMOS Active pixels, not only because of the lower allowable signal voltages, but also the larger noise voltages due to lower currents. In the thesis, we propose two new architectures, PMOS-reset APS and Complementary Active P...[ Read more ]

CMOS Active Pixel Sensor (APS) takes the advantage of the mature CMOS industry to compete with the Charge-Coupled Devices (CCD). The advantage of CMOS APS includes low supply voltage, high integration, and flexible functions. However, the scaling of conventional CMOS Active Pixel Sensors (APS) has been shown to be difficult. Besides process optimization issues, one of the major barrier in APS scaling is the limit on the available output swing at reduced power supply. Small output swing has an enormous impact on the signal-to-noise ratio and the dynamic range of the CMOS Active pixels, not only because of the lower allowable signal voltages, but also the larger noise voltages due to lower currents. In the thesis, we propose two new architectures, PMOS-reset APS and Complementary Active Pixel Sensor (CAPS) to overcome the limit of V_DD scaling. The design methodology and the trade-offs of the CAPS architecture in term of required power supply, available signal swing, power consumption, pixel size and fill factors with respect to a number of deep submicron technology generations are studied.

The PMOS-reset APS is implemented in a hybrid bulk/SOI CMOS active pixel image sensor, in which the photo-diode is build on the bottom substrate, while the reset transistor and the in-pixel amplifying transistor are built on the top silicon film. The performance of this APS is expected to be similar to the bulk technology with potentially higher speed due to the lower capacitance that the photodiode has to drive in SOI technology. At the same time, the doping of the SOI substrate can be arbitrarily low without affecting the CMOS circuit performance. The use of low doping can significantly increase the depletion width for the photo-diode beyond that achievable in bulk technology and leading to higher responsivity.

The CAPS pixel has been fabricated with a 0.25μm CMOS technology from TSMC and demonstrated to be functional at a V_DD below 1V with 0.55V output swing. To our knowledge, it is the first APS operating at such a low V_DD is reported. The pixel size is 12x10μm with a fill factor of 30%. Base on the CAPS array, we have build a 128 X 128 pixel image sensor with on-chip low voltage 8-bit analog-to-digital converter, correlated double sampling and digital control and timing. The output 8-bit digital data can be directly transferred to the computer. After the reconstruction and gamma correction of image code, the image can be displayed. This camera-on-a-chip implementation can be utilized in the low voltage high integrated imaging and vision system, such as web camera, surveillant system and vision device on the PDA’s, which need low voltage designs to extended battery life.