The combination of MILC and high temperature annealing process is very promising for TFT technology in realizing multilevel 3-D structures. However, the key to success of this method is the optimisation of process parameters and hence the grain size. In order to optimise the grain size, it requires a study on process conditions - temperature, time, metal concentration etc., that affect the crystallization process, grain size, grain boundaries and hence the performance of the device. Temperature and annealing time for crystallization are very important process parameters and need to be optimised....[ Read more ]

The combination of MILC and high temperature annealing process is very promising for TFT technology in realizing multilevel 3-D structures. However, the key to success of this method is the optimisation of process parameters and hence the grain size. In order to optimise the grain size, it requires a study on process conditions - temperature, time, metal concentration etc., that affect the crystallization process, grain size, grain boundaries and hence the performance of the device. Temperature and annealing time for crystallization are very important process parameters and need to be optimised.

In this thesis work, first material characterization of the metal induced laterally crystallized poly-silicon was performed and the effects of electric field, temperature and time were investigated. It was found that rate of crystallization could be remarkably enhanced in the presence of electric field. Also, electric field combined with the MILC leads to lower crystallization temperature and shortens the annealing time. Furthermore, the concept of ramp annealing was proposed and the effect of temperature and time was studied in detail. Also, the temperature and time for MILC was optimised during this study.

Finally, TFTs were fabricated and characterised at different MILC annealing temperatures with and without subsequent high temperature with only one extra mask added. It was found that TFT fabricated using optimised temperature and time shows the performance comparable to super TFT (SOI), thus shortens the annealing time to few hours (2-4 hours) with lower thermal budget. It is believed that super TFTs with SOI CMOS performance and good uniformity can be obtained through the reduction in channel dimensions and optimised process conditions.