Low Dropout Regulators (LDRs) are commonly used in high performance applications due to their low noise, fast transient response characteristics. In LDR design, frequency response is the most important issue in the regulator performance. With conventional LDR, the bandwidth varies with load current. Thus, the regulator cannot satisfy the speed specification for wide load current range. Besides, due to the compensation characteristics, this design is unreliable and imprecise for high performance application....[ Read more ]

Low Dropout Regulators (LDRs) are commonly used in high performance applications due to their low noise, fast transient response characteristics. In LDR design, frequency response is the most important issue in the regulator performance. With conventional LDR, the bandwidth varies with load current. Thus, the regulator cannot satisfy the speed specification for wide load current range. Besides, due to the compensation characteristics, this design is unreliable and imprecise for high performance application.

In this thesis, a new pole-zero tracking frequency compensation is proposed. A tracking zero is generated to cancel out the load current dependent pole. A low frequency dominant pole is also introduced to boost up the DC gain. With this compensation scheme, the frequency response becomes load current independent and the performance can be optimized for wide load current range. The precision is much higher due to the large DC loop gain. Reliability is ensured since the compensation only depends on well-controlled parameters and the ratio of the same component.

A LDR using the proposed frequency compensation scheme is designed using a 0.35 μm CMOS process. Load current varies from 0 μA to 100 mA. Simulation results show that the proposed design features a bandwidth variation of 2.5 times as opposed to over 10, 000 times in conventional design. The 96 dB minimum DC loop gain leads to an excellent line and load regulations of 0.67 mV/V and -0.43 μV/mA, respectively.

Finally, a low power version of the proposed LDR compensation scheme is designed and fabricated. The bandwidth variation is 2.3 times and the minimum DC gain is 72 dB. Measured line and load regulations are 0.5 mV/V and -6.1 μV/mA, respectively.