Area array technology is one of the main themes for IC packaging in the past decade. Ball grid array (BGA), chip scale package (CSP) and flip chip (FC) packages utilize solder ball (bumps) for interconnection overwhelmingly. Nowadays, the solder ball shear test has been widely used as a standard qualification test to evaluate the solder ball attachment strength for BGA, CSP and FC packages.
In this thesis, experimental observations of failure mechanisms in the solder ball shear test were performed on PBGA packages with 30-mil eutectic Pb-Sn solder balls at a fixed test condition. Three typical failure modes were identified. During the ball shear test, the solder ball undergoes substantial rigid-body rotation. For Mode I failure (the dominant mode), no crack is observed when the shear force starts to descend. For Mode II failure (the less dominant mode), a crack is initiated at the root of the solder ball at an early stage of the ball shear test. Finite element simulation on the ball shear test shows that Failure Modes I is closely related to the high regions of von Mises stress contours inside the solder.
The experimental investigation on effects of shear test conditions on solder ball shear strength for PBGA, CSP and FC packages were performed. A higher shear speed and lower ram height result in a higher solder ball shear strength. The shear strength of Sn-Ag-Cu solder balls is more sensitive to the shear speed than that of eutectic Pb-Sn solder balls. Finite element models were then constructed to simulate the effect of the shear test conditions on the solder ball shear strength for PBGA with 30-mil eutectic Pb-Sn solder balls. With a scale factor (effective thickness), it is feasible to study a 3-D problem with a 2-D finite element model. The results from 2-D modeling are in agreement with the experimental data. For BGA, CSP and FC, the ideal solder ball shear test conditions are recommended to be the cases with a ram height of 10 to 20% of the ball height and a shear speed in the range of 50 to 200 μm/s.
The solder ball shear strength of UltraCSP 80 remains stable till 4 time reflow. After that, the strength decreases significantly. For UItraCSPs with and without Au, with high temperature storage (HTS) at 150°C the shear strengths decrease monotonically. With HTS, the electrical resistances of UltraCSPs with and without Au increase monotonically. After 1000 hours, the resistance of UltraCSPs without Au levels off, while the resistance of UltraCSPs with Au continues to increase.
In the as-received state, the IMC forming at the interface of the solder and Al/Ni(V) / Cu UBM is in the Cu
6Sn
5 phase. After the reflow process of Au addition and with high temperature storage, two layers of (Cu,Au,Ni)
6Sn
5IMC with different Au and Ni amounts in them form finally. With the increase in HTS time, the IMC phase at the interface grows. After 1000 hours at 15O°C, the IMC growth rate in CSPs without Au slows down significantly, while the IMC phase in CSPs with Au continues to grow. For CSPs without Au, even after 2000 hours at 15O°C, solder balls still fail in the solder. For CSPs with 0.3wt% Au, brittle failure happens after 1000 hours at 15O°C, while brittle failure occurs after only 200 hours for CSPs with 0.5wt% Au. The changes of the solder ball shear strength and the electrical resistance are related to the microstructural evolution.
High temperature storage at 175°C was conducted on flip chip test dies with Sn-Ag-Cu solder bumps. After storage for only 24 hours at 175°C, both the solder bump shear strength and electrical resistance drop significantly. But from 100 to 2000 hours, the bump shear strength levels off, while the electrical resistance rises gradually at first and soon levels off as well. In the as-received state, all solder bumps fail in the bulk solder during the shear test. While after 20 hours at 175°C, brittle failure occurs. With high temperature storage, IMC at the interface transforms from Cu
6Sn
5 in the as-received state to a complex (Cu,Ni)
6Sn
5 phase.
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