The advances in communication technologies, especially the Wavelength Division Multiplexing (WDM) technology, have ensured a steady increase in the total data-rate of a single fiber. Current WDM systems offer 32-64 wavelengths at 2.5-10Gb/sec/wavelength, hence approaching 1 Tb/sec capacity, while research-level systems already exceed multi-terabits in a single fiber. As a result, switches/routers are replacing the fiber link as the bottleneck of the network. Consequently, there is a high demand for terabits/s switches/routers that support a large number of ports running at high bit rates. Most of these high-performance and scalable switches/routers employ crossbars as the switching fabric....[ Read more ]

The advances in communication technologies, especially the Wavelength Division Multiplexing (WDM) technology, have ensured a steady increase in the total data-rate of a single fiber. Current WDM systems offer 32-64 wavelengths at 2.5-10Gb/sec/wavelength, hence approaching 1 Tb/sec capacity, while research-level systems already exceed multi-terabits in a single fiber. As a result, switches/routers are replacing the fiber link as the bottleneck of the network. Consequently, there is a high demand for terabits/s switches/routers that support a large number of ports running at high bit rates. Most of these high-performance and scalable switches/routers employ crossbars as the switching fabric.

However, it is very challenging to implement a monolithic terabits/s CMOS crossbar switch chip. In particular, for a 256*256 crossbar switch, conventional approaches that use 8 bit-slices of switch core may not be feasible since the area is increased by a factor of 8. To address the problem, a novel 3-stage pipelined MUX-tree based architecture is proposed in this thesis. The clock cycle is reduced to below 1ns for a 0.25μm CMOS process implementation, so that only 2 bit-slices are needed for a 2Gb/s interface. Higher bit rates can be achieved if the CMOS process is scaled to a smaller dimension.

At the interface, asymmetric serial link architecture is adopted to decrease the complexity in the crossbar switch chip by removing the clock recovery circuits from the switch receiver end to the line card transmitter end. In this thesis, we enhance the architecture by eliminating the periodical calibration, and hence improving the performance without additional hardware cost.

Using TSMC 0.25μm CMOS technology, the crossbar switch chip is laid out and simulated to demonstrate and verify the design. Both 1ns clock cycle time in the crossbar switch core and 2Gb/s serial link at the interface are successfully achieved. The layout size of 256*256 crossbar switch is 18mm*18mm. It consumes 50W power and provides a total bandwidth of above half terabits/s.