Pattern formation in reaction diffusion mechanism implemented with a four layer CMOS cellular neural network
by Luo Tao
M.Phil. Electrical and Electronic Engineering
xi, 51 leaves : ill. ; 30 cm
The study of pattern formation in dynamic systems is a topic of interest to many areas of science and technology including biology, chemistry, fluids, plasmas, and nonlinear optics. Spatial pattern formation plays an important role, especially in biology....[ Read more ]
The study of pattern formation in dynamic systems is a topic of interest to many areas of science and technology including biology, chemistry, fluids, plasmas, and nonlinear optics. Spatial pattern formation plays an important role, especially in biology.
Reaction-Diffusion systems are good mechanisms to generate such spatial patterns. The patterns produced by this system are very stable over time, and self-supporting. In recent years, there have been many theoretical analyses on the reaction-diffusion model. Many possible applications have been discussed and simulated using digital computer. In recent work, some researchers discussed the possibility of implementing the reaction-diffusion mechanism at circuits level. Unfortunately, very few reaction-diffusion mechanism have been realized in VLSI.
Numerous theoretical and numerical simulation based studies have established that suitably connected Cellular Neural Networks (CNNs) are capable of exhibiting spatial and spatio-temporal patterns, as well as spatio-temporal chaos. While the CNN is not unique in this respect, as many systems of equations have been shown to exhibit such phenomena, one of the motivations for using the CNN to model these phenomena is its compatibility with VLSI technology. VLSI implementations of CNNs provide a well controlled physical substrate to study complex non-linear spatio-temporal dynamics in real time.
In this thesis, we propose and validate a model to implement reaction-diffusion mechanism in a VLSI chip for pattern formation based on cellular neural networks. The prototype was fabricated in HP 0.5 μm nwell process. It includes an array of 32 x 32 cells with a silicon area of 1982 x 3334 microns, power dissipation of 10.55 mw. The spatial patterns generated by the chip are bands of activity with a preferred width, which can be adjusted via external bias voltages.