In the past twenty years, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been scaled down continuously. The scaled transistors not only enable high integration density, high-speed and low-power circuits, but also reduce the cost per chip area. In order to keep improving the performance of electronic circuits and systems, the size of MOSFETs should be further scaled down....[ Read more ]

In the past twenty years, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) has been scaled down continuously. The scaled transistors not only enable high integration density, high-speed and low-power circuits, but also reduce the cost per chip area. In order to keep improving the performance of electronic circuits and systems, the size of MOSFETs should be further scaled down.

However, scaling MOSFETs into the deep sub-micron or even nano-scale regime while maintaining good control of short channel effect (SCE) is difficult, unless the innovative device structure such as double-gate MOSFET (DG-MOSFET) is adopted. SCE of DG-MOSFET is controlled by the employment of thin silicon channel, thin gate oxide and dual gate electrodes, which provides strong gate coupling to the channel and elimination of sub-surface leakage paths. Since the carriers are now confined in the thin silicon channel by two thin oxide layers, the quantum mechanical confinement effect should be accounted. Also, the use of thin gate oxide in DG devices leads to substantial direct tunneling gate current (DTGC) even in low voltage operation, which introduces significant standby power consumption.

In order to have a quantitative understanding on various scaling effects on the DTGC quantum mechanically, a simulator, which solves the Poisson and Schrodinger equations self-consistently including the effect of wavefunction penetration into gate dielectric and gate electrode, is developed in this thesis. The impacts of carrier confinement, different gate materials, silicon channel thickness scaling and gate oxide thickness scaling on DTGC are studied using the self-developed simulator. The effects of using high-k gate stack with and without an interfacial layer are investigated. Finally, the influences of drain bias and important small dimension effects such as velocity overshoot on the DTGC are also studied.