With CMOS devices scaling into the nanometer regime, further scaling of CMOS devices is becoming very difficult due to the fundamental limits in the areas of photolithography, process complexity, short channel effects, and interconnection delay. Novel device structures and technology architectures are necessary to address these problems. 3-D integration with multiple active layers is very promising for reducing the interconnection delay and increasing the packing density, and the major challenge of 3-D integration is to build a high quality Si film for the top active layers. Double-gate (DG) SOI (silicon-on-insulator) MOSFET is believed to have great potential for mainstream CMOS applications as the gate length is scaled into the nanometer regime. This is because the DG MOSFET provides...[ Read more ]

With CMOS devices scaling into the nanometer regime, further scaling of CMOS devices is becoming very difficult due to the fundamental limits in the areas of photolithography, process complexity, short channel effects, and interconnection delay. Novel device structures and technology architectures are necessary to address these problems. 3-D integration with multiple active layers is very promising for reducing the interconnection delay and increasing the packing density, and the major challenge of 3-D integration is to build a high quality Si film for the top active layers. Double-gate (DG) SOI (silicon-on-insulator) MOSFET is believed to have great potential for mainstream CMOS applications as the gate length is scaled into the nanometer regime. This is because the DG MOSFET provides reduced short channel effects and an ideal subthreshold slope. However, the really big challenge is to obtain a high quality thin SOI film for the implementation of the channel. Vertical MOSFET can provide high current drive and very short channel length without the need for expensive lithography; however, the high doping concentration in the body, which is required to suppress the short channel effects (SCEs) and punch-through, produces high threshold voltage and low effective mobility for sub-100nm devices.

To solve the problems mentioned above, several novel devices and technology are proposed in this thesis. First, a novel technology developed using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE) was proposed for 3-D IC implementation. A 3-D BiCMOS structure and a five-channel NMOSFET (FC-NMOS) were demonstrated using this technology. The 3-D BiCMOS structure not only saves the active area by 30%, but also provides a 23% reduction in propagation delay. The FC-NMOS implemented using the SEG/LSPE technology provides a 3.6 times higher current drive compared to that of the conventional bulk NMOS. Second, a novel double-gate (DG) SOI MOSFET built using the LSPE process was demonstrated. It provides the advantages of simple process and CMOS compatibility. Furthermore, it provides better V_T roll-off and DIBL characteristics compared to those of the single-gate MOSFET. Third, a novel ultra-thin vertical channel (UTVC) NMOSFET was designed and demonstrated. It can be easily scaled to a 50nm channel length without the need for expensive photolithography. The lightly doped ultra-thin vertical channel, obtained using solid phase epitaxy, can alleviate the effective mobility degradation and the short channel effects significantly. Finally, an UTVC CMOS technology with self-aligned asymmetric LDD was successfully implemented to demonstrate the usefulness of the UTVC technology for practical applications. These devices and technologies are very promising for the various high-density and high-speed ULSI applications.