Analog-to-digital converters (ADCs) play an essential role in modern RF receiver design. Traditional converters such as flash converters require high-precision analog components to achieve high resolution. As a result, Sigma-Delta (ΣΔ) modulators with oversampling and noise-shaping technique become an attractive alternative. The most important feature is that analog signals are converted using only a 1-bit ADC and digital-to-analog converter (DAC) to achieve high resolution and analog components may have a precision that is usually much lower than the resolution of the overall converter. In the past few years, many researches have been done on ΣΔ modulators for narrowband and wideband wireless receivers, since many applications require different data rates to transmit the information, a...[ Read more ]

Analog-to-digital converters (ADCs) play an essential role in modern RF receiver design. Traditional converters such as flash converters require high-precision analog components to achieve high resolution. As a result, Sigma-Delta (ΣΔ) modulators with oversampling and noise-shaping technique become an attractive alternative. The most important feature is that analog signals are converted using only a 1-bit ADC and digital-to-analog converter (DAC) to achieve high resolution and analog components may have a precision that is usually much lower than the resolution of the overall converter. In the past few years, many researches have been done on ΣΔ modulators for narrowband and wideband wireless receivers, since many applications require different data rates to transmit the information, and data converters that can operate for both narrowband and wideband applications.

In this project, a 3-V tri-mode double-sampling sixth-order switched-capacitor (SC) ΣΔ modulator with an intermediate frequency of 40 MHz will be described. A fast-settling double-sampled SC biquadratic filter architecture for high-speed operation is proposed. The three modes of operation are GSM (200k Hz), CDMA2000 (1.25 MHz) and WCDMA (3.84 MHz). To further increase system performance, extended noise-shaping technique is employed. The ΣΔ modulator has been implemented in TSMC 0.35 μm P2 CMOS technology. The simulation results show that the ΣΔ modulator achieves a SNR of 65.89/52.33/43.37 dB in 200k/1.25M/3.84 MHz. The power consumption is 294 mW and the chip area is 4.611 mm².