CMOS image sensors (CIS) take the advantage of the mature CMOS industry to compete with charge-coupled devices (CCD) in the digital imaging market. The advantage of CMOS image sensors includes low cost, low power, high integration and flexible functions. To day, the growth in the market of portable multimedia devices has generated an increasing demand for high density, low power CMOS image sensor systems. The target is expected to be met by the continuous technology scaling. However, CMOS processes are originally developed for high-performance generic logic circuits. To design a high-quality CMOS image sensor in the standard CMOS technology is not a straightforward task. Below 0.25μm CMOS technology, it is uncertain whether the advantage of the CMOS image sensor can be maintained. This...[ Read more ]

CMOS image sensors (CIS) take the advantage of the mature CMOS industry to compete with charge-coupled devices (CCD) in the digital imaging market. The advantage of CMOS image sensors includes low cost, low power, high integration and flexible functions. To day, the growth in the market of portable multimedia devices has generated an increasing demand for high density, low power CMOS image sensor systems. The target is expected to be met by the continuous technology scaling. However, CMOS processes are originally developed for high-performance generic logic circuits. To design a high-quality CMOS image sensor in the standard CMOS technology is not a straightforward task. Below 0.25μm CMOS technology, it is uncertain whether the advantage of the CMOS image sensor can be maintained. This motivates the study of a new CMOS digital imaging architecture design with the device scaling consideration presented in this thesis.

The major content of this study can be partitioned into four parts: (1) A thorough study on the CMOS device scaling and its impact on the performance of CMOS image sensors is first given with the SIA roadmap as a guideline; (2) A low voltage CMOS image sensor design methodology is developed to address the problems of the continuous reduction of voltage swings imposed by the device scaling, allowing the pixel to operate at an ultra-low supply voltage of 1.0V. A 128x128 test image sensor chip is designed and tested to verify its functionality; (3) The future SOI technology poses a great challenge to design a high performance CMOS image sensor on its ultra-thin silicon body. An innovative low voltage active pixel sensor (APS) fabricated on a silicon-on-sapphire (SOS) substrate is proposed to recover this performance with a number of unique features (4) A new digital pixel architecture is designed with a pixel-level A/D conversion and digital memory. It has the advantage of a highly scalability and high frame-rate. Those low voltage CMOS digital imaging architectures can be utilized in the low power and highly integrated portable imaging systems, which all need low voltage designs to extended the battery life.