Low power techniques on nanometer scale instruction bus and network-on-chip
by Siu-Kei Wong
M.Phil. Electrical and Electronic Engineering
xiii, 76 leaves : ill. ; 30 cm
Power consumption is the most challenging design constraint in the future VLSI circuit design. In this research work, we propose novel low power techniques on two different areas in VLSI circuit design. We propose a low power bus encoding scheme for the nanometer scale instruction bus and a low power routing methodology for the network-on-chip design....[ Read more ]
Power consumption is the most challenging design constraint in the future VLSI circuit design. In this research work, we propose novel low power techniques on two different areas in VLSI circuit design. We propose a low power bus encoding scheme for the nanometer scale instruction bus and a low power routing methodology for the network-on-chip design.
In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total bus capacitance loading and have a significant impact on the power consumption. Therefore, in the first part of this thesis, we will present two re-configurable bus encoding schemes, which are based on the correlation among the bit lines, to reduce the power consumption due to the cross coupling switching of the instruction buses. The instruction word is encoded by flipping and reordering the bit lines during compilation time to reduce the total switching capacitances. A crossbar is used to map back the data to the original instruction code before sending to the instruction decoder. The reordering can be re-configured during run-time by using different configurations of the crossbar. We propose two types of re-configuration, static and dynamic re-configuration. Static coding uses a fix flipping and re-configuring pattern after the corresponding program is compiled. Dynamic coding allows different re-configuring patterns during program execution. Experimental results show that by using the proposed schemes, significant energy reduction, 18-23%, can be achieved. Comparisons with existing bit lines reordering encoding scheme have also been made and on average more than 15% reduction can be obtained using our method.
In the second part of this thesis, we propose a routing algorithm which assigns a dedicated path for each communication task in the tile-based Network-On-Chip (NOC). The optimization goal is to minimize the total communication energy. In our proposed algorithm, adaptive voltage swing is assigned for each link among the routing path so that power can be reduced, and at the same time, the start time and end time of each communication task is scheduled. During the routing assignment, the performance constraint must be satisfied and the maximal bandwidth of the link cannot be exceeded. In order to solve this challenging routing problem, we divide the routing algorithm into two steps. The first step is to assign the start time, end time and voltage swing for each communication task and the second step is to find a low power routing path in the tile-based NOC. The scheduling of the start time and the end time, and the voltage swing assignment problem is formulated as a non-linear-programming (NLP) problem. The path-finding problem is formulated as a graph optimization problem. Experimental results show that by using this proposed routing algorithm, an average 62% energy reduction is achieved for random benchmarks and 57% energy reduction is achieved for a real-life multimedia application comparing with the original communication energy.
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