The double-gate (DG) MOSFETs have been identified in the International Technology Roadmap for Semiconductors (ITRS) as the most promising device structure that enables CMOS continuous scaling beyond the 65nm technology node (with 25nm physical gate length) for its higher drive current, improved sub-threshold swing, excellent short channel effect(SCE) control, and potential circuit design flexibility. Study of the process variation's impacts on performance are highly desirable to gain physical insight into the device's operating principles, facilitate the device designs, identify the key technological challenges to its fabrication and investigate the applications in circuitry. In this study, we focus on the process variations including the bottom gate misalignment issue in the planar st...[ Read more ]

The double-gate (DG) MOSFETs have been identified in the International Technology Roadmap for Semiconductors (ITRS) as the most promising device structure that enables CMOS continuous scaling beyond the 65nm technology node (with 25nm physical gate length) for its higher drive current, improved sub-threshold swing, excellent short channel effect(SCE) control, and potential circuit design flexibility. Study of the process variation's impacts on performance are highly desirable to gain physical insight into the device's operating principles, facilitate the device designs, identify the key technological challenges to its fabrication and investigate the applications in circuitry. In this study, we focus on the process variations including the bottom gate misalignment issue in the planar structures and the vertical non-uniformity of the finFET structures, In the planar double gate MOSFETs the bottom gate misalignment will cause the SCEs control to degrade. The SCEs-based double gate MOSFETs scaling theory should consequently be properly revised. The bottom gate misalignment also affects the circuit design and the layout design since the misalignment will induce larger parasitic parameters. The bottom gate misalignment effects on different double gate MOSFETs configurations and working modes are also different. Compared with the symmetric double gate MOSFETs, stricter misalignment accuracy is required for the double gate MOSFETs with asymmetric gate configurations. For the double gate MOSFETs with working mode of the ground plane, the tuning range of back gate bias is further limited by the bottom gate misalignment. FinFET is another highly potential device structure in the future. The vertical non-uniformity of the silicon fin may be a hidden risk causing device performance degradation. Proper considerations are necessary.