Design and integration of a single-chip 1-V CMOS IEEE 802.11a transceiver
by Leung Lai Kan
Ph.D. Electrical and Electronic Engineering
xv, 183 leaves : ill. ; 30 cm
Wireless local area network systems have received much attention in recent years. The market of wireless LAN systems has been booming so fast that the demand for low-cost, low-power and high-performance WLAN transceivers has grown dramatically. 2...[ Read more ]
Wireless local area network systems have received much attention in recent years. The market of wireless LAN systems has been booming so fast that the demand for low-cost, low-power and high-performance WLAN transceivers has grown dramatically.
In this dissertation, a 1-V CMOS frequency synthesizer for IEEE 802.11a is proposed by using a transformer-feedback VCO for low voltage and a stacked divider for low power. The novel design makes use of on-chip transformer and no other off-chip component is necessary. Implemented in 0.18μm CMOS process, the frequency synthesizer is operated with a 1V supply while consuming only 10mW and occupying an area of 1.28mm2. It measures a phase noise of -139dBc/Hz at an offset of 20MHz with a center frequency of 4.256GHz.
To further improve the performance of VCOs and frequency synthesizers in terms of tuning range, a novel technique to implement an integrated variable inductor using an on-chip transformer is also proposed. The design principle and optimization techniques are investigated. Employing such a variable inductor, a VCO is demonstrated to oscillate in 2 distinct frequency bands from 2.2GHz to 3.6GHz and from 10.7GHz to 11.3GHz. It consumes only 5mW with a 1V supply while occupying an area of 0.32mm2.
A 1-V CMOS IEEE 802.11a WLAN transceiver is also proposed. The aforementioned frequency synthesizer is integrated into the transceiver onto the same chip. The transceiver uses a zero-IF, dual-conversion topology. The receiving path includes all the building blocks from the LNA to the ADC and the transmitting path includes all the building blocks from the DAC to the PA. Fabricated in 0.18-μm CMOS process and operated at a single 1V supply, the receiver and the transmitter consume 85.7mW and 53.2mW, both including the frequency synthesizer. The total chip area with pads is 12.5 mm2.
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