The last decade has witnessed significant technological advancement of CMOS im-age sensors. CMOS imagers are undoubtedly gaining more territory when compared to their CCD counterparts. This is mainly due to their inherent advantages of low power, low cost and more importantly their ability to integrate image capture together with on-chip image processing. Deep sub-micron technologies have con-tributed significantly to paving the way to novel on-chip processing. The concept of "camera-on-a-chip" has already been introduced in the 90's and new development has seen more complex image processing. The recent emergence of new applica-tions in the area of wireless video sensor network and ultra low power biomedical applications have created new design challenges and frontiers requiring extensi...[ Read more ]

The last decade has witnessed significant technological advancement of CMOS im-age sensors. CMOS imagers are undoubtedly gaining more territory when compared to their CCD counterparts. This is mainly due to their inherent advantages of low power, low cost and more importantly their ability to integrate image capture together with on-chip image processing. Deep sub-micron technologies have con-tributed significantly to paving the way to novel on-chip processing. The concept of "camera-on-a-chip" has already been introduced in the 90's and new development has seen more complex image processing. The recent emergence of new applica-tions in the area of wireless video sensor network and ultra low power biomedical applications have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real-time while the hardware is constrained to take little physical space and to consume little power. This is only possible using custom sin-gle chip solutions integrating image sensor and hardware-friendly image processing algorithms.

In a conventional CMOS imager, images are read-out using a clock, which switches the multiplexer from one sensor to another, reading a voltage value from each and every sensor after a fixed integration interval. Images are therefore pro-duced by sequentially scanning the array using column and row scanners. Once the image is captured further image processing is performed by first buffering the entire frame before processing each frame sequentially. Conventional voltage mode scanning and sequential frame processing will soon fall short of meeting aggressive low power and high dynamic range requirements coupled with higher resolution and frame rate imagers. Therefore new approaches are required to overcome these limitations.

In this thesis, we explore new alternative ways to perform image capture and im-age processing using new encoding techniques. In contrast to conventional voltage mode encoding, we propose to perform image capture and image processing us-ing time-domain encoding inherently featuring wider dynamic range and immunity against continuous reduction of the supply voltage in deep submicron technologies. The thesis will explore both spiking and time-to-first spike (TFS) pixel architec-ture. The performance of time domain digital pixel sensor will be compared with arbitrated time-to-first spike pixel and potential scaling in deep submicron technolo-gies is also studied. A number of novel design concepts such as fair, high radix and pipelined arbitration are introduced in order to overcome the limitation of arbitrated image sensor array.

This work is further extended to show how a number of complex image processing operations can greatly benefit from time encoding. The inherent ordering property of the pixels' brightness at the output bus of the arbitrated TFS is exploited in order to significantly simplify the VLSI implementation of histogram equalization processing. A second case study of image processing is illustrated in image compression process-ing using an adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing. The image sensor chip together with the on-chip image compression processor have been implemented using 0.35μm CMOS technology and operates at 3.3V. Simulation and experimen-tal results show compression figures corresponding to 0.6-0.8 Bit-Per-Pixel, while maintaining reasonable PSNR levels and very low operating power consumption.

The thesis described the design of a very promising CMOS image sensor with built-in time-based image processing capabilities. It also raises the need for address-ing various new challenges such as timing errors at very high illumination levels, efficient external interfacing circuitry as well as improving the image quality in time based encoding. Resolving such issues will undoubtedly result in a very promising new generation of ultra-low power and smart vision sensors.