The implementation of the Copper/Low-dielectric constants (Cu/low-k) technology at the wafer level brings new challenges to electronic packaging. The more fragile low-k layer has poorer adhesive strength on the copper traces on silicon die that requires a greater deal of care in performing die bonding and tightens underfill selection criteria. The chip bonding process might induce stress which is higher than any wafer level process on the low-k layer. Preventing warpage in order to avoid too much stress on the silicon die becomes one of most important criteria in the selection of underfill. A new failure mode on the Cu/low-k layer has to be handled. This urged a review on the applicability of the conventional failure analysis techniques used in the electronic packaging industry. Howeve...[ Read more ]

The implementation of the Copper/Low-dielectric constants (Cu/low-k) technology at the wafer level brings new challenges to electronic packaging. The more fragile low-k layer has poorer adhesive strength on the copper traces on silicon die that requires a greater deal of care in performing die bonding and tightens underfill selection criteria. The chip bonding process might induce stress which is higher than any wafer level process on the low-k layer. Preventing warpage in order to avoid too much stress on the silicon die becomes one of most important criteria in the selection of underfill. A new failure mode on the Cu/low-k layer has to be handled. This urged a review on the applicability of the conventional failure analysis techniques used in the electronic packaging industry. However, literature review provided limited data and information regarding these new challenges. In addition, some of these literatures did not reveal sufficient information regarding the experimental setup and testing vehicles. As a result, the reader might be misled by the either too simplified or contradicting conclusions. In view of that, an integrated study of these new challenges on the implementation of Cu/low-k die specifying on the Flip Chip Ball Grid Array (FCBGA) was conducted. The generally proposed packaging and underfill selection criteria for FCBGA using Cu/low-k die were reviewed. Conventional mechanical polishing technique was analyzed and optimized. Underfills specified for that application and advanced plastic substrates from the market were characterized. Cu/low-k dices were flipped and dispensed with the underfills selected by the reviewed criteria. The assembled FCBGA were then tested under the temperature cycles to determine the reliability of the packages. Finally, several conventional failure analyses techniques were applied to determine the failure mode. The correlation of these failure modes to the underfill properties was also discussed.