The widespead of today’s digital imaging applications, especially the portable devices, require the integration of image capture, processing, and transmission with limited power budget. Intensive data acquisition, storage, and processing are required by most imaging devices for storing and transmitting high quality images. Image compression dramatically decreases the memory requirements for image data storage and transmission however it is very computationally demanding. Recently, some on-chip prototypes for image compression have been proposed, which in some cases include image sensors. Unfortunately, the prospect of implementing low power image acquisition and image compression on a single chip is limited by the fact that in order to achieve medium-to-high compression ratio and decent...[ Read more ]

The widespead of today’s digital imaging applications, especially the portable devices, require the integration of image capture, processing, and transmission with limited power budget. Intensive data acquisition, storage, and processing are required by most imaging devices for storing and transmitting high quality images. Image compression dramatically decreases the memory requirements for image data storage and transmission however it is very computationally demanding. Recently, some on-chip prototypes for image compression have been proposed, which in some cases include image sensors. Unfortunately, the prospect of implementing low power image acquisition and image compression on a single chip is limited by the fact that in order to achieve medium-to-high compression ratio and decent image quality, usually very complicated coding schemes are required. In this work, several hardware-friendly image compression algorithms that can be integrated into CMOS image sensor are investigated, simulated, and finally implemented in hardware.

A Differential Pulse Code Modulation (DPCM) system is proposed to efficiently eliminate the spatial redundancy of a captured image by changing its diverged histogram to a more converged form. By subtrating a pixel intensity with its prediction value, the distribution of the resulting residual signal can be modeled as a Gaussian distribution. The residual signal then is then quantized through an adaptive quantizer called the Fast Boundary Adaptation Rule (FBAR), which adapts the quantization boundaries according to the statistics of the incoming signals. The output of the FBAR quantizer will then be further compressed through a window-based lossless compression scheme called the Quadrant Tree Decomposition. This algorithm decomposes a captured image into four quadrants and further decomposes each of the quadrants into four sub-quadrants. This decomposition is carried out until reaching the pixel level. The outputs of the quantizer within a quadrant will be compared: if the values within a quadrant are the same, there will be no need to send all the data out through the channel provided that the decoder recognizes the structure of the Quadrant Tree. To implement this decomposition process, a quadrant based scanning pattern should be followed. Morton Z scan and Hilbert scan are two possible candidates that are explored and their performance are compared. The proposed algorithms are then validated through on-chip implementation using 0.35 CMOS technology. Experimental results shown 0.6bpp and 30dB are achievable while maintaining very low complexity and lw power consumption.

The last part of this thesis, explores using Vector Quantization (VQ) to perform quadrant-based compression. VQ quantizes a cluster or a block of data instead of quantizing the image data pixel by pixel. This is a lossy compression scheme that can achieve much better reconstructed image quality than the scalar quantization under the same bit rate. The combination of the VQ scheme and the DPCM system will be studied. Very good PSNR result for pretty low bit rate is achieved through simple block based predictive coding.