It is generally accepted that Complementary Metal-Oxide Semiconductor (CMOS) image sensors will take the place of their Charge Couple Device (CCD) counterparts and become the core of next generation on-chip visual system. This is mainly true because of CMOS on-chip processing capabilities and low power operation allowing the integration of image capture with on-chip processing. In conventional CMOS imagers, global clock signal is employed to scan the whole image sensors array in a certain manner (eg., Raster Scan or Mortan-Z Scan). The output voltage swing on each pixel, which is proportional to the incident light intensity, is therefore scanned and readout one by one. However, this traditional scan and read out method fails to meet the requirement of low power consumption and high dyna...[ Read more ]

It is generally accepted that Complementary Metal-Oxide Semiconductor (CMOS) image sensors will take the place of their Charge Couple Device (CCD) counterparts and become the core of next generation on-chip visual system. This is mainly true because of CMOS on-chip processing capabilities and low power operation allowing the integration of image capture with on-chip processing. In conventional CMOS imagers, global clock signal is employed to scan the whole image sensors array in a certain manner (eg., Raster Scan or Mortan-Z Scan). The output voltage swing on each pixel, which is proportional to the incident light intensity, is therefore scanned and readout one by one. However, this traditional scan and read out method fails to meet the requirement of low power consumption and high dynamic range especially in high resolution and high frame rate video applications.

In this thesis, we propose a CMOS imager based on time domain image encoding and Address Event Representation (AER). Asynchronous read-out protocol is employed to eliminate the need for global scanning clock signal. Moreover, Conditional Replenishment as well as Fast Boundary Adaptation Rule quantization are used to compress the sensor's output data and enhance the channel efficiency. Image capture and on-the-fly video processing is thus achieved. The imager has been implemented using 0.35μm CMOS technology. Results show that 0.68bpp can be achieved while average PSNR of 35.22dB is maintained.

Address Event Representation (AER) is further exploited in order to build a novel self-powered time domain CMOS imager. In this imager, the energy of incident light is used to power the operation of the imager, thus reducing the power consumption from traditional power supply V_dd, which makes this idea very attractive for ultra-lower power consumption applications. A sensor prototype is built and implemented using 0.35μm CMOS technology. The power generation and dissipation process is analyzed in detail. A self-powered imager model has been built, indicating that self-power concept is especially attractive for time domain AER imagers.