In performance driven layout design, parasitic components need to be evaluated with a reasonable degree of accuracy. The dominant layout capacitances and resistances in CMOS integrated circuits are highly correlated with the structures of MOS gate and source/drain regions. Therefore, a physical model including layout/geometry effects of arbitrary configurations is essential. In this thesis, high-frequency models for planar bulk and non-planar SOI MOSFETs are developed. A wide range of devices are investigated, from conventional multi-finger MOSFETs, to enhanced compact waffle MOSFETs, and to three-dimensional multi-gate devices for next-generation circuit blocks....[ Read more ]

In performance driven layout design, parasitic components need to be evaluated with a reasonable degree of accuracy. The dominant layout capacitances and resistances in CMOS integrated circuits are highly correlated with the structures of MOS gate and source/drain regions. Therefore, a physical model including layout/geometry effects of arbitrary configurations is essential. In this thesis, high-frequency models for planar bulk and non-planar SOI MOSFETs are developed. A wide range of devices are investigated, from conventional multi-finger MOSFETs, to enhanced compact waffle MOSFETs, and to three-dimensional multi-gate devices for next-generation circuit blocks.

For planar bulk CMOS devices, a small-signal model including parasitic components is analyzed, which can be used to predict RF figures of merits (cut-off frequency ƒ_T, oscillation frequency ƒ_max, minimum noise figure NF_min, etc.) for both compact waffle layouts and conventional RF CMOS layouts. The validity of the small-signal model is verified through device fabrication and high-frequency scattering parameter measurement. In addition, the advantages of the compact waffle layout are demonstrated by the implementation of low-noise amplifiers, passive mixers and wide-band transmit/receive (T/R) switches in a 0.35-μm standard processing technology.

When CMOS technologies advance into nano-scale regime, researchers have been studying non-planar multi-gate silicon-on-insulator (SOI) MOSFETs for their superior capability of suppressing the short-channel effects (SCEs). However, their three-dimensional nature complicates the relationship between parasitic components and device geometrical parameters such as fin spacing, fin height and polysilicon thickness. In this thesis, an equivalent gate-resistance model derived from distributed R-C networks is established and verified using a 2-D MEDICI simulator. Also, a layout-oriented optimization guideline is derived to achieve the minimum gate resistance. For parasitic fringing and overlap capacitances in non-planar SOI multi-gate devices, a physical method based on a system transformation named conformal mapping is proposed catering to the gate architecture. Moreover, the proposed models for parasitics are embedded into a core MOS model, and the multi-gate compact model is implemented in an analog/mixed-signal simulation environment. The combination of extrinsic and intrinsic models is capable of predicting the transient and frequency responses of non-planar multi-gate MOS devices accurately in high frequency applications.