Design and integration of a single-chip CMOS transceiver for passive UHF RFID readers
by Wang Wenting
Ph.D. Electronic and Computer Engineering
1 v. (various leaves) : ill. ; 30 cm
In this thesis, a single-chip CMOS UHF RFID reader is implemented for passive RFID systems operated in 860MHz to 960MHz, which integrates a RF transceiver including IQ data converters and digital baseband....[ Read more ]
In this thesis, a single-chip CMOS UHF RFID reader is implemented for passive RFID systems operated in 860MHz to 960MHz, which integrates a RF transceiver including IQ data converters and digital baseband.
Firstly, the distinctive features of RFID systems are analyzed, system and building block specifications are derived based on the EPCglobal Gen-2 standard. It is revealed that key challenges in implementing the RFID reader are self-interference caused by simultaneous transmitting and receiving at the same carrier frequency, as well as reconfigurability for multi-protocol operation. The goal of this project is to build systems that support multiple standards with multiple data rates and multiple modulation formats in different electromagnetic environment by a flexible system architecture.
As one of the critical building blocks, a low power low phase noise fractional-N frequency synthesizer is proposed. By properly distributing the capacitance between drain and source of a transformer-feedback VCO, the modified VCO exhibits enhancement in tank Q factor, as well as benefits from the noise filtering of even harmonics. A 3rd order 2-bit single-loop ΣΔ modulator is optimized for the proposed synthesizer so that it achieves the optimization of phase noise and power consumption at the architecture level. In addition, the detailed design consideration, circuit implementation and theoretical analysis for a power-optimized reconfigurable baseband are presented, which is crucial for a multi-protocol RFID reader. It allows power optimization for different system bandwidth and interference scenarios.
Fabricated in 0.18μm CMOS technology, the proposed RFID reader occupies a chip area of 18.8mm2. The synthesizer achieves the phase noise of –76dBc/Hz in-band and –126dBc/Hz at 1-MHz offset with a reference spur of –84dBc. For the listen mode operation with LNA turned on, the RX front-end measures P-1dB of –9.4dBm and IIP3 of 0dBm. The worst-case RX sensitivity is –90dBm for an output SNR of 11dB for all the bandwidths from 80 KHz to 1 MHz. In the talk mode with LNA bypassed, the RX front-end measures P-1dB of 3.5dBm, IIP3 of 18dBm. RX sensitivity is –70dBm in the presence of –5dBm self-interferer. The TX achieves output P-1dB of 10.4dBm and sideband rejection ratio of –53.6dBc. With maximum interference rejection ability, RX baseband power can be dynamically optimized from 63mW at 640kbps to around 6.2mW at 40kbps. It corresponds to a total RX power of 105.6mW to 47.8mW. The proposed RFID reader dissipates a maximum power of 249mW when transmitting maximum output power of 10.4dBm and receiving the tag’s response of –70dBm in the presence of –5dBm self-interferer.
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