Driven by increasing demand of short-range and high-data-rate wireless communications, ultra-wideband (UWB) technology with target data rates up to 480Mb/s within 10-meter distance becomes more and more attractive. The UWB system utilizes the unlicensed 3.1 – 10.6 GHz frequency band with a transmit power below the FCC limit of -41.25 dBm/MHz. According to MultiBand OFDM Alliance SIG proposal, the UWB spectrum is divided into 14 bands, each with a bandwidth of 528 MHz. In this dissertation, the design and integration of a single-chip CMOS transceiver for Multi-Band OFDM (MB-OFDM) UWB system covering the first 9 frequency bands from 3.1 GHz to 8.0 GHz is presented....[ Read more ]

Driven by increasing demand of short-range and high-data-rate wireless communications, ultra-wideband (UWB) technology with target data rates up to 480Mb/s within 10-meter distance becomes more and more attractive. The UWB system utilizes the unlicensed 3.1 – 10.6 GHz frequency band with a transmit power below the FCC limit of -41.25 dBm/MHz. According to MultiBand OFDM Alliance SIG proposal, the UWB spectrum is divided into 14 bands, each with a bandwidth of 528 MHz. In this dissertation, the design and integration of a single-chip CMOS transceiver for Multi-Band OFDM (MB-OFDM) UWB system covering the first 9 frequency bands from 3.1 GHz to 8.0 GHz is presented.

Firstly, from the system point of view, dual-conversion zero-IF2 transceiver architecture is proposed. The proposed frequency scheme makes use of the upper-sideband oscillation LO1 to achieve the required image suppression without additional filtering. The system requirements of the transceiver are discussed based on which the detailed specifications of all the building blocks are derived and verified.

Next, in terms of circuit design and implementation, a fully-integrated synthesizer is proposed employing single-sideband mixers to generate the two required LO signals. Proposed design techniques include a modified transformer-coupled quadrature VCO, a single-sideband mixer with an ultra-wideband inductive-network loading, and long-metal-line loading-insensitive layout technique. In addition, injection-locked divider techniques with different input configurations are proposed and analyzed. Specifically, a double-balanced quadrature-input quadrature-output regenerative divider and two ultra-low-voltage dividers with transformer-feedback or transformer-coupling are developed.

Design and measurements of the other building blocks in the fully-integrated transceiver, namely LNA, mixers, LPF, VGA, ADC, and DAC, will also be briefly introduced. Finally, the single-chip integration and the complete measurement results of both the receiver and the transmitter in a 0.18um CMOS process will be presented and discussed. The receiver measures maximum S11 of -13dB, maximum NF of 8.25 dB, in-band IIP3 of better than -13.7 dBm, and variable gain from 25.3 to 84.0 dB. IQ path gain and phase mismatch of the receiver chain are measured to be 0.8 dB and 4° respectively. The transmitter achieves a minimum output P-1dB of -8.2 dBm, sideband rejection of better than -42.2 dBc, and LO leakage of smaller than -46.5 dBc.