With the anticipation of increasing system demands, the need to integrate multiple functions (e.g. digital, analog, high voltage, etc.) on a single chip has become apparent. Power integrated circuits (PICs) combining high-voltage, high-current output devices with low-voltage logic and control elements have improved performance and reliability, and reduced cost and system size compared to the discrete approach. A major issue for the design of this kind of circuits is the substrate cross-talk between adjacent devices that prevents normal operation through latch-up mechanism. Some basic solutions for isolation in PICs, such as the traditional p-n junction isolation (JI) and the dielectric isolation (DI), have been proposed. Among the two, JI requires large silicon area and suffers from la...[ Read more ]

With the anticipation of increasing system demands, the need to integrate multiple functions (e.g. digital, analog, high voltage, etc.) on a single chip has become apparent. Power integrated circuits (PICs) combining high-voltage, high-current output devices with low-voltage logic and control elements have improved performance and reliability, and reduced cost and system size compared to the discrete approach. A major issue for the design of this kind of circuits is the substrate cross-talk between adjacent devices that prevents normal operation through latch-up mechanism. Some basic solutions for isolation in PICs, such as the traditional p-n junction isolation (JI) and the dielectric isolation (DI), have been proposed. Among the two, JI requires large silicon area and suffers from large leakage current at severe conditions. Although the superiority of DI offered by silicon-on-insulator (SOI) technology results in a much smaller chip area and minimum leakage currents, the higher wafer cost and lower heat dissipation capability limit its use only to niche applications.

In this thesis, a novel isolation structure with ultra-deep trench and backside etching is proposed. It can achieve complete isolation with low wafer cost, reduced isolation area, and high heat dissipation capability. First, the design and operation of the novel isolation structure as well as the 2-D device and thermal simulation results is discussed. Then, the layout design and fabrication process for experimental characterization of the novel isolation structure are presented. Finally, experimental techniques for characterizing the electrical and thermal performance of the devices in both the novel isolation structure and SOl are presented. The simulation and experimental results show that the novel isolation structure can provide complete isolation as that of the SOl isolation structure, but with an average of 26% improvement on heat capability during the power device turn-off transient with short gate pulse duration. After the system is heated more, the heat capability of the novel isolation structure is not as good as that of the SOI isolation structure due to the low thermal conductivity of the air gap underneath the power device. However, this novel isolation technology offers a potential cost reduction of 5X to 10X compared to the SOl technology.