CMOS image sensors are widely used in low power portable image capture devices, such as digital cameras, game stations and mobile phones. Indeed, with the aggressive scaling of CMOS technologies, high performance, and low cost camera-on-chip solutions are becoming a reality. Recently, Pulse Width Modulation (PWM) Digital Pixel Sensor (DPS) has seen an increased attention. Conventionally PWM DPS composes of a photodiode, on pixel analog to digital converter (ADC), and memory elements. This offers the advantage of parallel operation in the DPS array enabling high frame-rate. However, the silicon area of the embedded memory elements impacts the pixel size greatly and increases the challenge of pixel-level routing. This influences the fill factor of each pixel, and the density of the array....[ Read more ]

CMOS image sensors are widely used in low power portable image capture devices, such as digital cameras, game stations and mobile phones. Indeed, with the aggressive scaling of CMOS technologies, high performance, and low cost camera-on-chip solutions are becoming a reality. Recently, Pulse Width Modulation (PWM) Digital Pixel Sensor (DPS) has seen an increased attention. Conventionally PWM DPS composes of a photodiode, on pixel analog to digital converter (ADC), and memory elements. This offers the advantage of parallel operation in the DPS array enabling high frame-rate. However, the silicon area of the embedded memory elements impacts the pixel size greatly and increases the challenge of pixel-level routing. This influences the fill factor of each pixel, and the density of the array.

In this thesis, dynamic memory (DRAM) is proposed to substitute the static memory (SRAM) which is conventionally used on the PWM DPS. The memory area to pixel area ratio is successfully reduced from 65% to 20%. In addition, Multi-Reset Integration scheme (MRI) is introduced to reduce the requirement of the memory elements on PWM DPS (down to only 1-bit). Trade-offs between the integration time and the pixel memory requirement are studied and a mathematical analysis model is developed. Using the MRI scheme, a 4-bit full CMOS 2T-DRAM is proposed to be embedded in each pixel while an 8-bit resolution is achieved. Comparing with the DPS without using MRI scheme, a 60% reduction in pixel size is achieved while the frame rate is slightly decreased by 6%. The power consumption on the critical path of the DPS system is also studied. The on-pixel ADC is shown to be the bottleneck and is proposed to be replaced with the latch-based ADC. The average static power consumption of a pixel is reduced from 5μW to 0.005μW. A single-ended sensing circuit is proposed for the 2T-DRAM readout instead of the commonly used differential sensing circuit. The pixel level routing overhead is therefore reduced as the requirement of the reference bit-lines are eliminated.