Polycrystalline silicon conductivity modulated thin film transistors
by Anish Kumar K.P
THESIS
1997
Ph.D. Electrical and Electronic Engineering
xvii, 133 leaves : ill. ; 30 cm
Abstract
Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) on glass has received significant attention for use in large area microelectronic applications. These applications include both niche and large volume applications such as printer drivers, image scanners, active-matrix liquid crystal displays (AMLCDs), electro-luminescent displays, plasma assisted displays, etc. Currently, the leading technology for these applications is amorphous-Si (a-Si) TFT. However, as the information content increases, a-Si technology encounters severe challenges due to its inherent low mobility, high parasitic capacitance, low aperture ratio, and non-compatibility to CMOS process. On the other hand, poly-Si technology offers high mobility, low parasitic capacitance, small size, CMOS compatibility, goo...[ Read more ]
Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) on glass has received significant attention for use in large area microelectronic applications. These applications include both niche and large volume applications such as printer drivers, image scanners, active-matrix liquid crystal displays (AMLCDs), electro-luminescent displays, plasma assisted displays, etc. Currently, the leading technology for these applications is amorphous-Si (a-Si) TFT. However, as the information content increases, a-Si technology encounters severe challenges due to its inherent low mobility, high parasitic capacitance, low aperture ratio, and non-compatibility to CMOS process. On the other hand, poly-Si technology offers high mobility, low parasitic capacitance, small size, CMOS compatibility, good stability, and uses the infrastructure of silicon science and technology. Thus, a simple low temperature poly-Si technology which allows large area system integration on panel will be in great demand for future high definition displays. However, it was found that poly-Si material properties vary with its method of preparation, its grain size, its surface roughness, and the nature and distribution of the inter-granular and bulk defects. Therefore, extensive studies are needed to optimize the key parameters such as the off-current, on-current, and breakdown voltage of the devices. These parameters can be optimized by means of material preparation as well as innovative device designs. In this thesis, three TFT structures were invented and fabricated using a simple low temperature poly-Si technology. With these novel structures, pixels, pixel drivers, and analog and digital peripheral circuits can all be built on the same glass substrate. This allows the ultimate goal of display systems on glass to be much more closer to reality.
First, a high voltage transistor called the Conductivity Modulated Thin Film Transistor (CMTFT) is presented. Using this structure, the fundamental current pinching problem of the conventional high voltage offset drain TFT is completely eliminated. Experimental results show that the CMTFT can handle three orders of magnitude higher current than that of the conventional offset drain TFT while still providing low leakage current, high breakdown voltage, and fast switching speed. It is very suitable to be used as pixel drivers and high voltage printer drivers.
In order to implement efficient pixel transistors and design analog peripheral circuits on glass, a second novel structure called the double-gate Elevated-Channel Thin Film Transistor (ECTFT) is invented. The ECTFT exhibits kink-free IV characteristics and low leakage current compared to the conventional uniform thin- and thick-film devices. Furthermore, the double-gate operation of the device provides much higher output current, high on/off current ratio, and steeper subthreshold slope compared to the uniform film devices. All of these result in efficient pixels and high performance analog devices to be built on glass.
Finally, to further optimize the CMTFT using the ECTFT technology, a third novel structure called the double-gate Elevated Channel CMTFT (EC-CMTFT) is fabricated. Combining the advantages of elevated channel and conductivity modulation, the EC-CMTF'T has a four times reduction in offset region resistance and a five times larger on/off current ratio compared to the CMTFTs.
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