THESIS
2017
xii, that is xiv pages, 156 pages : illustrations ; 30 cm
Abstract
Fueled by unprecedented growth in mobile internet, multimedia and cloud computing
applications, modern communication networks must support increasingly higher data rates. To
achieve this, wireless standards have evolved to become more spectrally efficient by adopting
increasingly complex modulation schemes and exploiting wider channel bandwidths which
present significant design challenges to the frequency synthesizer of a wireless transceiver. This
thesis presents a number of circuit and system level frequency synthesis techniques to improve
the output frequency range and spectral purity of multi-band CMOS frequency synthesizers.
The first part of this thesis proposes a reconfigurable dual-band and concurrent oscillator
capable of generating harmonically unrelated tones in two f...[
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Fueled by unprecedented growth in mobile internet, multimedia and cloud computing
applications, modern communication networks must support increasingly higher data rates. To
achieve this, wireless standards have evolved to become more spectrally efficient by adopting
increasingly complex modulation schemes and exploiting wider channel bandwidths which
present significant design challenges to the frequency synthesizer of a wireless transceiver. This
thesis presents a number of circuit and system level frequency synthesis techniques to improve
the output frequency range and spectral purity of multi-band CMOS frequency synthesizers.
The first part of this thesis proposes a reconfigurable dual-band and concurrent oscillator
capable of generating harmonically unrelated tones in two frequency bands, 4.7-6.6GHz and 8.5-10.7GHz, either concurrently or one-at-a-time for multi-band radio applications. Such an
oscillator can be used for inter-band carrier aggregation resulting in an effectively wider channel.
By controlling the discrimination property of a cross-coupled pair, stable coexistence of the two
tones is demonstrated to be possible using a single CMOS gm-cell for the first time.
The second part focuses on improving the spectral purity and frequency resolution of
wideband inductor-less injection-locked PLLs. A wideband phase-domain filtering technique
capable of up to 20dB phase-noise and spur suppression is proposed. Additionally, a capacitor-ring
coupled oscillator reduces delay-cell mismatches while increasing the number of phases
available for injection. Demonstrated in 65nm CMOS, the prototype 1.2GHz synthesizer
improves high-frequency phase noise from -115 to - 135dBc/Hz @10MHz, injection spurs from
40.5dBc to -57dBc, integrated jitter from 3.57ps to 1.48ps, and frequency resolution from
48MHz to 2MHz allowing for an inductor-less alternatives to LC-based PLLs in wireless
applications.
Finally, the design of a millimeter-wave (mmW) sub-harmonic injection-locked (SHIL)
fractional-N frequency synthesizer for wireless multi-band point-to-point backhaul
communications is presented. The locking range of injection-locked frequency multipliers
(ILFMs) are significantly widened due to a proposed 0° rippled phase response and a highly
efficient 3
rd-harmonic injection current generation technique. Based on this wide locking-range
ILFM chain and a dual-modulus divider, a modified SHIL architecture is further proposed to
significantly relax the oscillator design trade-offs to simultaneously achieves an excellent output
phase noise between -107dBc/Hz and -113.9dBc/Hz @1MHz offset over a wide output
frequency range from 20.6GHz to 48.2GHz with a fine frequency resolution of 220kHz while
consuming 148mW of power. This architecture allows costly mmW frequency calibration loops
required in conventional SHIL-PLLs to be completely removed.
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