THESIS
2020
xi leaves, 49 pages : illustrations ; 30 cm
Abstract
Video processing applications always demand extremely low latency to guarantee
real-time performance. Traditional deployment routines on CPU platform with a standard
open-source library such as OpenCV may fail to satisfy this requirement because of
the slow transfer rate of large-size images between the disk and processors, and the poor
capability of parallel computing. CPU-FPGA heterogeneous platforms, which combines
the advantages of both components, provide a solution for fast and efficient implementations
of such applications.
With the advent of heterogeneous computing platform, hardware libraries become a
trend for vision application deployment. However, template-based design focuses only on
configurable hardware architectures, which hinders fine-grained optimization and o...[
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Video processing applications always demand extremely low latency to guarantee
real-time performance. Traditional deployment routines on CPU platform with a standard
open-source library such as OpenCV may fail to satisfy this requirement because of
the slow transfer rate of large-size images between the disk and processors, and the poor
capability of parallel computing. CPU-FPGA heterogeneous platforms, which combines
the advantages of both components, provide a solution for fast and efficient implementations
of such applications.
With the advent of heterogeneous computing platform, hardware libraries become a
trend for vision application deployment. However, template-based design focuses only on
configurable hardware architectures, which hinders fine-grained optimization and often
fails to tap hardware’s acceleration potential. In this thesis, We investigate a recent
proposed joint HSV-LPQ object tracking algorithm as a case study. We analyze the
algorithm and propose a novel accelerators. We optimize not only the algorithm but
also the hardware architecture where the algorithm is implemented on. We also design
a self-adaptive size adjust function to reduce data transfer size. Our design outperforms
the CPU- and library- based design, indicating the potential of further acceleration.
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