Antenna is necessary for any wireless transmitter or receiver. As the carrier frequencies of the signal increase and enter the mm-wave range, the size of an antenna is comparable to that of a silicon chip, therefore integrating antennas in silicon is possible. While on-chip antennas have the merits of high integration level and low cost in mass production, their antenna gains and radiation efficiencies are usually low because of the low resistivity silicon substrate.

In this thesis, a 60GHz on-chip antenna with a cross AMC pattern in 28nm CMOS process is proposed. A cross AMC pattern with a novel zigzag placement is proposed and simulated to reduce the substrate loss of the silicon. A dipole antenna is optimized for this process and put on the top metal layer while the proposed AMC patt...[ Read more ]

Antenna is necessary for any wireless transmitter or receiver. As the carrier frequencies of the signal increase and enter the mm-wave range, the size of an antenna is comparable to that of a silicon chip, therefore integrating antennas in silicon is possible. While on-chip antennas have the merits of high integration level and low cost in mass production, their antenna gains and radiation efficiencies are usually low because of the low resistivity silicon substrate.

In this thesis, a 60GHz on-chip antenna with a cross AMC pattern in 28nm CMOS process is proposed. A cross AMC pattern with a novel zigzag placement is proposed and simulated to reduce the substrate loss of the silicon. A dipole antenna is optimized for this process and put on the top metal layer while the proposed AMC pattern is put between the antenna and the substrate. The antenna structure has a peak gain of 0.4dBi and an efficiency of 35%.

Besides, the practical considerations for integrating an on-chip antenna to the frontend circuits are seldom discussed. When the antenna is integrated with other circuits on-chip, the position, clearance, area, impedance matching and layout design rules are critical. Design flow and the compromises made throughout are presented. The final antenna structure has a fixed area of 1.5mm*0.8mm and a peak gain of -3.2dBi.

Finally, a detailed testing plan for various measurements is presented. The antenna is planned be measured by direct probing. However, the probe being close to the antenna under test might detune it. As a back-up plan, the antenna could also be evaluated using an on-chip mixer. By mixing down the 60GHz RF signal to 10MHz, bondwire connections and PCB SMA interface could be used with negligible effects. Antenna gain and phase mismatch between antenna outputs could also be observed in time domain at low frequencies. To accommodate these separate measurements, a plan for trimming traces is provided.