There is an increasing trend in using digital control in power management over the analog control as the digital control allows easier system integration with the advance of digital fabrication technology. With the well-developed automated design tools for a digital system and the easy re-programmability of the digital system, the time-to-market of a digital power management product is short and this is highly desirable in todays electronic industry....[ Read more ]

There is an increasing trend in using digital control in power management over the analog control as the digital control allows easier system integration with the advance of digital fabrication technology. With the well-developed automated design tools for a digital system and the easy re-programmability of the digital system, the time-to-market of a digital power management product is short and this is highly desirable in todays electronic industry.

Many different advanced current-mode control methodologies have been proposed for “integrated” digital-control switching converter. However, most of them are based on two external ADCs and expensive DSP/FPGA. Due to high power consumption of the external ADCs and DSP, they cannot be used in a low power application.

This thesis introduces a fully integrated current-mode digital controller with a single ADC for low power applications. The controller consists of a novel low power Time-Multiplex (TM) ADC, Digital Pulse with modulator (DPWM) and the digital compensators. Together with the maximum current rating of 500mA power MOSFETs, all of them are integrated in a single silicon chip with the area of 1049μm×1833μm in 0.35μm technology.

The novel TM-ADC makes use of the time-multiplex scheme and the advantage of the simple and power-efficient Successive Approximation ADC to quantize both output voltage and inductor current to digital signals. It consumes current at the rate of 11μA/MHz and the conversion time is 100ns. The TM-ADC has been verified experimentally for quantizing both output voltage and the inductor current.

A modified Delay-Lock-Loop (DLL) DPWM with 3MHz operating frequency has been developed for minimizing the mismatch of the delay-cell. This enables the modified DPWM to operate in higher frequency without losing conversion accuracy.

A new algorithm has also been proposed for implementing a Look-Up-Table approach of realizing the digital compensators. This algorithm uses a reduced set of table entry to recreate the full set of original table entry. By using this algorithm, approximately 20% chip area can be reduced for implementing the digital compensators.

Lastly, the digital-control buck converter has been implemented in a standard CMOS 0.35μm process and its function has been verified through both simulations and experiments. Measurement results show the buck converter is stable with different operation condition with maximum power efficiency of about 85%.