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CMOS image sensor technology is developing rapidly as the device feature size is continuously being scaled down with the trend that strictly following the Moore's Law. Current-mediated CMOS imager is one kind of current-mode APS imagers, which is widely investigated in recent years. However, the current-mediated CMOS imager suffers from high power consumption and low linearity due to the second order distortion, which is un-affordable for the Mega-pixel imager design.

The previous scheme to reduce the power consumption was reported by adopting an array-level reset/read-out technique. By such a strategy, the power consumption is independent on the array size. However, this low-power feature comes with the cost of extra pixel size, lower fill factor and more complicated control circuit.

Based on the low-power array-level reset/read-out scheme, we propose a novel pixel structure. The number of in-pixel transistors is reduced from 6 for the previously reported design to 4. The in-pixel control signal lines are greatly simplified from original 4 control bit lines to only 2, by which the in-pixel wiring overhead is significantly eliminated. Additionally, a linearization circuit is adopted making use of the short channel effect. According to the analysis and simulation result, the linear range is extended up to 50%.

A test imager with the proposed scheme was fabricated using an AMS 0.35um CMOS process. Measurement results show proper functionalities with improved performances compared with the previously reported design.

Moreover, a linear-output and ultra-low power current-mediated imager scheme was proposed in this thesis, by using the feature of operating in triode region instead of in saturation region. Finally, a VCO based read-out scheme was described and analyzed, which theoretically promising a low-noise performance.