Among the three configurations of field-effect transistors that incorporating carbon nanotubes (CNT) as current pathways, aligned CNT array transistors outperform single tube structures due to the capability of good reproducibility and the possibility of cost-effective mass production, and overshadow random networks because of the absence of massive inter-tube junctions in current transport channels. In this thesis, we report the fabrication and characterization of horizontally aligned CNT array transistors....[ Read more ]

Among the three configurations of field-effect transistors that incorporating carbon nanotubes (CNT) as current pathways, aligned CNT array transistors outperform single tube structures due to the capability of good reproducibility and the possibility of cost-effective mass production, and overshadow random networks because of the absence of massive inter-tube junctions in current transport channels. In this thesis, we report the fabrication and characterization of horizontally aligned CNT array transistors.

A commonly used method to fabricate CNT is CVD, either thermal CVD or PECVD, with the assistance of catalyst. Catalyst is one significant factor that affects CNT growth results, such as uniformity of CNT diameters, wall numbers, and density. Therefore, the impact of catalyst thickness and catalyst areal fraction on CNT growth were investigated.

The as-grown CNT using CVD are vertically aligned due to crowding effect. We introduced a leveling process leveraging capillary effect to convert the vertical CNT into horizontal CNT. By combining with electron-shading effect to confine the initial inclination of CNT, we could achieve horizontal CNT with arbitrary orientations on Si substrate.

With the readily available horizontal CNT arrays, we introduced four fabrication processes of CNT array transistors on Si substrates. Preliminary electrical measurements results indicate that the on-chip grown CNT are dense and more suitable for interconnect applications while the transferred CNT with low site density of 2~3 tubes/μm were better choice for transistor structures.

We then carried out systematic electrical characterization of CNT array transistors fabricated with transfer process, with the widths varying from 1 μm to 50 μm, and lengths from 1 μm to 10 μm. Our bottom-gated transistors with Ti/Au as source/drain electrodes perform as p-type transistors. Scaling property investigation illustrated a good reproducibility and controllability of our devices. The on-state current were found to be proportional to device width and inversely proportional to device length. We then conducted electrical breakdown process to remove the metallic CNT from the bundles for the purpose of on/off current ratio improvement. This process effectively improved the on/off ratio by 2~3 orders.

We also studied 1/f noise in CNT array transistors. The noise amplitude coefficient was found to be inversely proportional to total carrier numbers, and directly proportional to device resistance, A = 7.12×10^-11R. Both discoveries are in good consistence with Hooge’s empirical relation for classical devices.