Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications, such as wireless sensor nodes, designing a low power and low energy ADC is one of the major challenges. For an SA-ADC, the dominant power dissipation sources are the comparator and the switching in the DAC capacitor array....[ Read more ]

Successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications, such as wireless sensor nodes, designing a low power and low energy ADC is one of the major challenges. For an SA-ADC, the dominant power dissipation sources are the comparator and the switching in the DAC capacitor array.

We propose a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant and the least significant bits, and using two different capacitor arrays with unequal sizes to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Experiments were carried out on a 10-bit SAR-ADC, designed using a TSMC 0.18μm CMOS process. HSPICE simulations show that a significant reduction in energy consumption is achieved using the proposed design. We also demonstrated the operation in a pipelined architecture to achieve higher throughput without the need of duplication of the DAC capacitor arrays.

We also propose a novel architecture of an ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, μC_OX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits for measuring the transistor characteristics. Monte Carlo post-layout HSPICE simulations were carried out with 100 samples to evaluate the performance of the comparator latch. Experimental results show that when compared with state-of-the-art pre-amplifier-less architectures, the standard deviation of the input voltage offset is reduced by more than 75% over a range of 400mV difference in the common mode input voltage.