Non-volatile memory is an important part in low-power portable electronics such as PDA, mobile phone, digital camera as well as recently booming RFID. Recently development in such devices, especially digital camera, has spurred the need of high density non-volatile memory storage with reasonable cost. This can only be achieved by continuation of flash memory cell scaling, which is the mostly used non-volatile memory nowadays. However, the scaling of Flash memory cell has always been lagging behind that of logic CMOS due to the tight constrain in the lower limit of the gate dielectric and the existence of floating gate in floating-gate type memory cell....[ Read more ]

Non-volatile memory is an important part in low-power portable electronics such as PDA, mobile phone, digital camera as well as recently booming RFID. Recently development in such devices, especially digital camera, has spurred the need of high density non-volatile memory storage with reasonable cost. This can only be achieved by continuation of flash memory cell scaling, which is the mostly used non-volatile memory nowadays. However, the scaling of Flash memory cell has always been lagging behind that of logic CMOS due to the tight constrain in the lower limit of the gate dielectric and the existence of floating gate in floating-gate type memory cell.

In this study, a 2-D analytical model of the channel potential in the floating-gate flash memory cell is developed to study the effect of the floating-gate on the device scaling and it is found that the impact of the floating-gate increases with device scaling. To ensure the continuation of flash memory cell scaling, the interpoly capacitance must be increased which spurs the need of improved inter-poly dielectric performance. Conventionally, the inter-poly dielectric has always been of inferior quality due to the surface roughness as well as the existence of grain boundaries on the poly-Silicon floating gate. To improve the situation, two methods, CMP (Chemical-Mechanical Polish) and MILC (Metal Induced Lateral Crystallization), are developed to allow the formation of high quality dielectric on top of the floating gate. With the improved dielectric, it is believed that the scaling beyond l00nm can be achieved.