Fully-Depleted Silicon-On-Insulator (FDSOI) technology has emerged as a potential substrate for Ultra Large Scale Integration(ULSI). Devices on SOI have reduced short channel effects, higher mobility and higher transconductance, reduced junction capacitance, near ideal subthreshold slopes, reduced hot carrier effects and good radiation hardness. Moreover, device fabrication on SOI is simpler than Bulk technology due to no wells, no latch-up and near perfect isolation. Furthermore SOI technology is also suitable for high temperature operation due to less leakage current. Accurate device models are necessary for better device design and circuit simulation. Also potential devices on new technology must be characterized for device and circuit design, in particular, the growing need for mixe...[ Read more ]

Fully-Depleted Silicon-On-Insulator (FDSOI) technology has emerged as a potential substrate for Ultra Large Scale Integration(ULSI). Devices on SOI have reduced short channel effects, higher mobility and higher transconductance, reduced junction capacitance, near ideal subthreshold slopes, reduced hot carrier effects and good radiation hardness. Moreover, device fabrication on SOI is simpler than Bulk technology due to no wells, no latch-up and near perfect isolation. Furthermore SOI technology is also suitable for high temperature operation due to less leakage current. Accurate device models are necessary for better device design and circuit simulation. Also potential devices on new technology must be characterized for device and circuit design, in particular, the growing need for mixed signal circuits and BiCMOS. Towards achieving these novel goals, this thesis addressed several important issues in FDSOI technology such as SPICE level device modeling, Hot Carrier Effects, device degradation and device characterization.

First part of the thesis reviews currently available device models on SOI and presents a new threshold voltage model and a DC MOSFET model suitable for analog and digital circuit simulation. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy, model continuity and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, careful consideration is given to parasitic source/drain resistance, kink effect and self-heating. The accuracy of the model is validated with experimental data and found to be in good agreement.

Second part of the thesis deals with impact of scaling silicon film thickness (an important device parameter) on Hot Carrier Effects and device reliability. A new understanding on Hot Carrier Effects(HCE) in FDSOI technology is presented. Increasing drain electric field with reducing SOI film thickness is reported for the first time using gate current measurements. Conflicting results reported between device simulation and experiments about drain electric field dependence on SOI film thickness are resolved. The presence of large series parasitic source/ drain resistance (R[subscritp ds]) is the main cause for decreasing drain electric field with reducing SOI film thickness. A simple model is presented to explain the effect of R_ds on gate current measurements. This provided a consistent explanation and an unified understanding on hot carrier effects versus silicon film thickness scaling in FDSOI technology. Furthermore this basic understanding has simplified modeling hot carrier effects in FDSOI MOSFETs.

FDSOI technology must also address the hot carrier induced device reliability and device design trade-offs for improving reliability. In this context it is important to understand the underlaying physics which cause device degradation. Unfortunately there is no consensus on hot carrier degradation issues in FDSOI devices. This is due to insufficient capability of existing . degradation characterization methods. To provide a more complete understanding on hot carrier degradation, a novel methodology is proposed. Traditionally measured front gate threshold voltage shift, decoupled front gate and back gate threshold voltage shifts are measured in the new methodology. Interpretation of the experimental results are presented on floating body, bipolar breakdown and R_ds debiasing effect on hot carrier degradation. Based on the experimental observations, a phenomenological model for FDSOI N-Channel MOSFET degradation is also provided.

Third part of the thesis deals with characterization of Lateral Bipolar Transistors on SOI(SOILBT). A good bipolar device on SOI greatly enhances its suitability to mixed signal and BiCMOS applications. Perfect isolation between devices in SOI technology can be exploited in the above mentioned application. However, the presence buried oxide and its effects on SOILBT performance is important to understand. A buried oxide induced punchthrough is presented for the first time in addition to the punchthrough due to dopant segregation. Experimental evidence for buried oxide induced punchthrough and 2-D numerical simulation results to support the evidence are presented. Simple measurement techniques are proposed to characterize SOILBTs and the dopant segregation in the buried oxide using parasitic MOSFET present in SOILBT. Design curves for minimum base width of SOILBT are also obtained to avoid buried oxide induced punchthrough using 2-D simulations.

Final part of the thesis deals with device design guidelines for FDSOI CMOS technology. Using experimental data and 2-D numerical simulation, optimum V_dd/V_th ratio, transistor sizing, optimum buried thickness and front gate thickness are obtained for minimum inverter delay and energy-delay product. Finally, FDSOI guidelines are compared with bulk technology device design guidelines for low power applications