Digital visual communication has been a fast growing industry during recent years. Efficient and cost-effective VLSI implementation of video compression is essential for the proliferation of visual communication and video services. In this thesis, we will discuss the issue of cost-effective VLSI implementation for video compression. The discussions are based on five design parameters, i.e., algorithmic performance, processing speed, silicon area, I/O bandwidth, and power consumption. Four parts are presented in this thesis which focus on the algorithm and VLSI architecture design for block-matching motion estimation (BMME) and fractal coding techniques. In Part 1, we show that the cost-effective VLSI design can be achieved using efficient VLSI architectures. Three VLSI architectures are...[ Read more ]

Digital visual communication has been a fast growing industry during recent years. Efficient and cost-effective VLSI implementation of video compression is essential for the proliferation of visual communication and video services. In this thesis, we will discuss the issue of cost-effective VLSI implementation for video compression. The discussions are based on five design parameters, i.e., algorithmic performance, processing speed, silicon area, I/O bandwidth, and power consumption. Four parts are presented in this thesis which focus on the algorithm and VLSI architecture design for block-matching motion estimation (BMME) and fractal coding techniques. In Part 1, we show that the cost-effective VLSI design can be achieved using efficient VLSI architectures. Three VLSI architectures are proposed for different video applications. In Part 2, we discuss cost-effective VLSI design using efficient BMME algorithms. To do so, we propose two BMME algorithms which are very suitable for VLSI implemen-tation. In Part 3, we consider the cost effective VLSI design using truncated pixels. We investigate the system performance with different number of trun-cated bits for BMME. As a result, the hardware cost can be drastically reduced without sacrificing the system performance. In this part, we also discuss the issue of power consumption in VLSI design. We propose a novel method for reducing power consumption of BMME by adaptively changing the pixel reso-lution during the computation of the motion vectors. In Part 4, efficient VLSI architectures for fractal coding are discussed. By estimating the number of re-quired gates, the proposed architecture can be implemented in a single chip with the state-of-the-art VLSI technology.