The development of Silicon-on-Insulator (SOI) materials, processes and circuits has advanced dramatically over the past one decade, making SOI a serious alternative to the bulk CMOS technology. This dissertation investigates the physical effects presented in SO1 MOSFET related to low-noise and low-power applications. ₂...[ Read more ]

The development of Silicon-on-Insulator (SOI) materials, processes and circuits has advanced dramatically over the past one decade, making SOI a serious alternative to the bulk CMOS technology. This dissertation investigates the physical effects presented in SO1 MOSFET related to low-noise and low-power applications.

The performance advantage of SOI is attributed to the buried-oxide layer. However, SiO₂ inhibits heat dissipation in the Si film and leads to the self-heating effect (SHE). This research proposes a methodology for the extraction of SHE parameters. With SHE parameters known, a compact SOI device model with SHE-free model parameters can be easily obtained.

In addition to SHE, the buried-oxide gives rise to the floating-body effect (FBE). The shot noise in the neutral body is amplified and filtered by FBE, leading to an excess noise at low frequency. The total drain current noise is the superposition of flicker noise and a Lorentzian-like excess noise. A physical yet compact low-frequency noise model is presented.

Thermal noise is the major component at high frequency. The lattice temperature is higher than ambient temperature as a result of SHE. Furthermore, the carrier temperature near the drain end increases substantially due to the high electrical field. A physical thermal noise model for SOI MOSFET is developed considering both lattice temperature and carrier temperature.

Low-noise amplifiers (LNA) composed of floating-body (FB) and body-tie (BT) SOI devices are designed and tested. The LNA's operate at 1.8-GHz under 1.5-V power supply. A complete high-frequency noise model for LNA is developed.

Dynamic Threshold-Voltage MOSFET (DTMOS) on SOI technology is supposed to be a promising candidate for extremely low-power circuits. The parasitic diode leakage of SOI DTMOS is studied and a complete power dissipation model for SOI DTMOS inverter is proposed based on 2D simulation.