As the radio paging system is upgraded from POCSAG to the high speed FLEX or ERMES protocol, both the modulation level and the baud rate are increased. What is unchanged is the available bandwidth. Consequently, the modulation index is decreased and additional difficulties are imposed on the design of a direct-conversion receiver. The main problems are (1) there are no mature demodulation techniques available for zero-IF M-ary FSK signals, and (2) the signal contains strong DC/low-frequency energy and hence DC offset cancellation is no longer an easy task....[ Read more ]

As the radio paging system is upgraded from POCSAG to the high speed FLEX or ERMES protocol, both the modulation level and the baud rate are increased. What is unchanged is the available bandwidth. Consequently, the modulation index is decreased and additional difficulties are imposed on the design of a direct-conversion receiver. The main problems are (1) there are no mature demodulation techniques available for zero-IF M-ary FSK signals, and (2) the signal contains strong DC/low-frequency energy and hence DC offset cancellation is no longer an easy task.

In this dissertation, a direct-conversion receiver is designed for high speed 4FSK radio paging applications. Various design considerations are discussed and analyzed. A zero-crossing based counting/comparing scheme is chosen for the demodulation. The BER is improved by a novel zero-crossing interpolation technique. Following official specifications on radio paging receivers, a high level simulation is carried out to verify the demodulator performance and derive circuit requirements. The self-mixing-related time-varying offset is suppressed by the harmonic mixer to the noise level. A differential peak alignment method is developed to cancel the mismatch-induced static offset. A frame-by-frame scheme is also proposed for further offset reduction.

A prototype receiver is fabricated in a 0.35 micron CMOS process, with all major building blocks included. The front-end consists of a differential LNA and a quadrature harmonic mixer. In the base-band, an AGC circuit provides over 30 dB gain tuning range. The channel selection is done by a 5th order gyrator filter. The demodulator is formed by a l-level zero-crossing interpolator, clock recovery circuits and decision logics. Main functions of the receiver has been verified.