This dissertation demonstrates a monolithic 900-MHz CMOS wireless transceiver. Single-conversion architecture with a high-IF of 70 MHz is chosen for the receiver and direct modulation architecture is chosen for the transmitter to save components, to maximize the image rejection, and to minimize the chip area....[ Read more ]

This dissertation demonstrates a monolithic 900-MHz CMOS wireless transceiver. Single-conversion architecture with a high-IF of 70 MHz is chosen for the receiver and direct modulation architecture is chosen for the transmitter to save components, to maximize the image rejection, and to minimize the chip area.

The transceiver integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, an image-rejection RF filter with a notch filter, a fully-integrated fractional-N frequency synthesizer with sigma-delta modulation, image-rejection mixers, phase shifters, a high-Q channel-selection IF filter, a variable-gain amplifier with continuous-time offset cancellation, a band-pass sigma-delta analog-to-digital converter and a class-E power amplifier.

The proposed transceiver has been designed and fabricated with 0.5μm CMOS process. The measurement of the whole transceiver has been completed. The image rejection, noise figure and linearity of the receiver are high enough to achieve a sensitivity of -90 dBm.

This research confirms that a standard CMOS process can be used to implement a fully monolithic transceiver for short-distance wireless communications.