The flip chip packaging has become one of the most popular electronics packaging technologies for all kinds of applications. For high end applications like central processing units (CPU), the flip chip packaging technology demonstrates its distinctive advantage of high efficiency to dissipate heat from the silicon chip. Flip chip packages have also received tremendous interests for low end applications such as watch modules and smart card due to their light weight and thin package profiles for low cost applications. Fiber reinforced organic substrates are commonly employed to lower the material costs. This raises concerns on mechanical and thermal mismatches between the silicon chip and the organic substrate. The consequence is that there are significant stress concentrations in the sol...[ Read more ]

The flip chip packaging has become one of the most popular electronics packaging technologies for all kinds of applications. For high end applications like central processing units (CPU), the flip chip packaging technology demonstrates its distinctive advantage of high efficiency to dissipate heat from the silicon chip. Flip chip packages have also received tremendous interests for low end applications such as watch modules and smart card due to their light weight and thin package profiles for low cost applications. Fiber reinforced organic substrates are commonly employed to lower the material costs. This raises concerns on mechanical and thermal mismatches between the silicon chip and the organic substrate. The consequence is that there are significant stress concentrations in the solder joints due to the difference in dimensional changes between the silicon chip and the organic substrate during thermal cycles. To reduce the relative displacements and to redistribute the stress over the entire package, an underfill resin is encapsulated along the gap between the chip and the substrate as a stress buffer. The introduction of an underfill in the package also raises other reliability issues, for example, weak interfacial adhesion between package components, process-induced residual stress as during assembly, proper selection of component materials etc.

The objective of the present thesis is to gain some new insights into the above underfill-related reliability issues in flip chip packages. To measure the interfacial adhesion between the underfill and other package components, the button shear tests were performed and the corresponding failure behaviors were characterized. The correlations between the elements obtained from X-ray photoelectron spectroscopy (XPS) and the thermodynamic characteristics determined from the contact angle measurement were established. The UV/Ozone treatment on the polymeric soldermask surface offered the possibility of further enhancement of the adhesion with the underfill material. The interfacial adhesion between the underfill and other components were also characterized. The interfacial adhesion of underfill with eutectic solder was far weaker than the other interfaces, indicating the necessity to treat the solder surface to improve the bond. Incomplete filling of the underfill, either due to flux residue, entrapped gas altered the mode of solder joint failure from hydrostatic fatigue cracking to plastic deformation. An optimized UV/Ozone treatment on polymeric soldermask surface enhanced the interfacial bond strength with underfill resin.

The bi-material strip bending (BMSB) method has been successfully developed to in-situ monitor the evolution of the residual stresses in epoxy-based underfill resins during curing and thermal cycles. The residual stress in the silica filled conventional underfill was higher than that of the rubber modified no-flow underfill. The importance of the properties of underfill, such as modulus and coefficient of thermal expansion (CTE), in governing its residual stress after cure were discussed. Isothermal contraction of epoxy is also noticed during thermal cycles at temperature below the glass transition temperature.

The numerical model based on the time-temperature dependent underfill material is compared with that based on the linear elastic underfill material. The importance of material properties of package components, such as the moduli and CTEs of the underfill, solder and PCB, in reducing the stress concentrations is highlighted. The effect of process-induced defects in the underfill layers is also studied. Thermo-elastic modeling of underfill behavior underestimate the stress and strain levels in the solder joints, due to the underestimate of the relaxation of polymeric underfill. The rigidity of PCB substrate also influenced significantly the lifetime of solder interconnection.

Keywords: Flip Chip Package, Underfill, Contact Angle Method, Residual Stress Measurement, Viscoelasticity, Finite Element Analysis