Portable electronic equipment including cellular phones, laptop computers and a variety of hand-held electronic devices has increased the need for efficient voltage regulation to prolong battery life. Low-dropout linear regulators, known as LDOs, have gained popularity with the growth of these applications since they offer inexpensive, reliable solutions and require few components or little board area compared to the switching-mode counterparts.

Due to the low-power design in digital applications, the power supply voltage is expected to decrease in the near future. However, the threshold voltage is not expected to decrease as rapidly as the physical size. It is difficult to design mixed-signal circuits, including the design of low-voltage LDO and voltage reference. In order to solve...[ Read more ]

Portable electronic equipment including cellular phones, laptop computers and a variety of hand-held electronic devices has increased the need for efficient voltage regulation to prolong battery life. Low-dropout linear regulators, known as LDOs, have gained popularity with the growth of these applications since they offer inexpensive, reliable solutions and require few components or little board area compared to the switching-mode counterparts.

Due to the low-power design in digital applications, the power supply voltage is expected to decrease in the near future. However, the threshold voltage is not expected to decrease as rapidly as the physical size. It is difficult to design mixed-signal circuits, including the design of low-voltage LDO and voltage reference. In order to solve the low-voltage design limitation of LDO without compromising the performance, solutions have been proposed but require BiCMOS process and more external components. Currently, low-voltage LDO and voltage reference implemented in standard CMOS technologies without using non-standard circuit devices such as lateral BJT, depletion MOS transistors and low-threshold-voltage MOS transistors, are not available. Moreover, conventional pole-zero cancellation compensation scheme in LDO design limits the loop-gain bandwidth and thus degrades the steady-state and transient performances. The off-chip output capacitor, which is required to stabilize the conventional LDOs, also hinder the inclusion of LDO in system-on-chip design.

In this thesis, a novel structure of LDO based on a three-stage amplifier structure is proposed to provide a high-performance LDO. A novel compensation scheme, Damping-Factor-Control frequency compensation, is developed to provide LDO with high stability and wide loop-gain bandwidth. In addition, a low-voltage CMOS voltage reference is developed to provide a low-temperature-drift reference voltage to define the LDO output voltage.

Based on the above proposed technique, a 1.5-V 100-mA CMOS LDO, which is implemented in a standard 0.6-μm CMOS technology, is developed. The supply current is 38 μA and the occupied chip area is 779 μm x 919 μm, including pads. The LDO has high stability under line and load changes in either presence or absence of an output capacitance. The no-capacitor feature of the LDO is particularly suitable for system-on-chip applications. The LDO provides a total line and load regulation of less than ±0.25% with a temperature coefficient of 38 ppm/°C. Moreover, the output voltage can settle within 2 μs for full load transients. The power supply rejection ratio at 1 MHz is better than -30 dB, and the output noise at 100 Hz is less than 2 μV / √Hz.