Three dimensional packaging (3DP) is emerging as the solution for microelectronics development toward system in package (SIP). 3D die stacking either with flip chip bonding or with wire bonding has a very good potential for the implementation of 3D packaging. With the new interconnection materials Cu introduced in this advanced packaging, special attention should be paid to Cu-to-Si diffusion due to the fast diffusion of Cu in Si and impact of Cu on the silicon devices....[ Read more ]

Three dimensional packaging (3DP) is emerging as the solution for microelectronics development toward system in package (SIP). 3D die stacking either with flip chip bonding or with wire bonding has a very good potential for the implementation of 3D packaging. With the new interconnection materials Cu introduced in this advanced packaging, special attention should be paid to Cu-to-Si diffusion due to the fast diffusion of Cu in Si and impact of Cu on the silicon devices.

In this study, the Cu-to-Si diffusion in through silicon vias (TSVs) and in wire bonding are investigated. The interlayers for TSVs with sidewall multilayer and for wire bonding with bonding pad layers are characterized. Firstly secondary ion mass spectrometry (SIMS) depth profiling is implemented for the Cu-to-Si diffusion analysis. The standard Cu/Si samples are prepared for SIMS depth profile verification. Compared with the finite element model (FEM) analysis results, the Cu diffusivity determined by SIMS analysis is in good agreement with FEM analysis. For the flip chip bonding, through silicon vias (TSVs) are adopted as vertical interconnection within the silicon die. The TSVs formation method, namely, deep reactive ion etching (DRIE), is evaluated. The experimental results and comparisons in terms of via uniformity, aspect ratio dependent etching, undercutting, and effects of various mask materials are discussed in detail for sub-micron silicon via. To prevent Cu diffusion, improve the Cu adhesion and provide electrical insulation, the interfacial multilayer is deposited on the TSVs sidewall. Regarding Cu-to-Si diffusion, the effects of Si surface roughness, insulation layer, barrier layer and the Cu source supply are investigated. The phase transition during thermal annealing is studied. Experimental results show that the SiO₂ layer not only serves for electrical insulation, but also helps to maintain the integrity of the Ti barrier layer and to prevent further diffusion of Cu into the silicon. From a surface roughness comparative study, the experimental results show that a rougher silicon surface may promote Cu diffusion depth and subsequently will impose a higher threat on the IC devices. Therefore, a smooth surface is preferred for the deposition of interfacial multilayers on the sidewall of TSVs. The Ti barrier layer in the interfacial multilayer structure on a smooth silicon substrate can effectively prevent Cu diffusion at an annealing temperature lower than 300℃. However, when the annealing temperature is raised to 300℃ or above, the barrier layer tends to breakdown and the Cu element will surpass the Ti layer. It is also identified that the Cu layer thickness may affect the Cu diffusion depth. In general, a thicker Cu layer will promote the Cu diffusion depth. This effect reveals that the Cu diffusion in TSVs for 3D packaging should be different from that in the Cu damascene structure for on-chip interconnection. Furthermore, from X-ray diffraction (XRD), Energy Dispersive X-ray (EDX) analysis, scanning electron microscopy (SEM) results, Cu₃Si is found when the barrier layer fails for the Cu/Ti/Si structure. Sheet resistance measurement and surface roughness measurement indicate the growth of the copper grains during thermal annealing and also the strong reaction and diffusion in the interfacial multilayer at high annealing temperatures. To effectively control the copper diffusion in TSVs, the thickness of different layers in the interfacial multilayer structure should be optimized. The influential rank of different layers is studied by design of experiment (DOE). The results indicate that Si roughness is the first important impact factor. Therefore, a smaller Si roughness is preferred. Because the Si roughness is smaller for smaller TSVs by DRIE, the TSVs size should be balanced between the Cu diffusion and TSVs fabrication feasibility. Secondly, SiO₂ is more important than TaN within their factor levels. Due to the low cost of SiO₂, a thick SiO₂ layer should be adopted rather than a thick TaN layer. Furthermore, thicker Cu film thickness will improve Cu diffusion depth and impose more threats to silicon devices.

For Cu-to-Si diffusion in wire bonding, the effects of a TiW barrier layer, A1 pad deformation, Cu source supply and different bonding wire materials are studied. Experimental results indicate that aluminum pad deformation will induce more Cu-to-Si diffusion and the amount of Cu supply may promote the diffusion of Cu into Si. With the addition of the TiW barrier layer, Cu and Au diffusion into Si have been decreased. Comparison between Cu and Au bonded samples shows that Cu diffuses more in Si than Au, which may impose more threat to silicon devices. With the optimization of the Cu bonding process and appropriate selection of pad layer structure, devices with Cu wire bonding should have a better performance and reliability than Au wire bonding.